boards/nucleo-f334/include/periph_conf.h
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1 /*
2  * Copyright (C) 2015 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
22 #ifndef PERIPH_CONF_H
23 #define PERIPH_CONF_H
24 
25 #include "periph_cpu.h"
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30 
38 /* give the target core clock (HCLK) frequency [in Hz],
39  * maximum: 72MHz */
40 #define CLOCK_CORECLOCK (72000000U)
41 /* 0: no external high speed crystal available
42  * else: actual crystal frequency [in Hz] */
43 #define CLOCK_HSE (8000000U)
44 /* 0: no external low speed crystal available,
45  * 1: external crystal available (always 32.768kHz) */
46 #define CLOCK_LSE (1)
47 /* peripheral clock setup */
48 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
49 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
50 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
51 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
52 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
53 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
54 
55 /* PLL factors */
56 #define CLOCK_PLL_PREDIV (1)
57 #define CLOCK_PLL_MUL (9)
58 
64 static const timer_conf_t timer_config[] = {
65  {
66  .dev = TIM2,
67  .max = 0xffffffff,
68  .rcc_mask = RCC_APB1ENR_TIM2EN,
69  .bus = APB1,
70  .irqn = TIM2_IRQn
71  }
72 };
73 
74 #define TIMER_0_ISR (isr_tim2)
75 
76 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
77 
83 static const uart_conf_t uart_config[] = {
84  {
85  .dev = USART2,
86  .rcc_mask = RCC_APB1ENR_USART2EN,
87  .rx_pin = GPIO_PIN(PORT_A, 3),
88  .tx_pin = GPIO_PIN(PORT_A, 2),
89  .rx_af = GPIO_AF7,
90  .tx_af = GPIO_AF7,
91  .bus = APB1,
92  .irqn = USART2_IRQn
93  }
94 };
95 
96 #define UART_0_ISR (isr_usart2)
97 
98 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
99 
105 static const pwm_conf_t pwm_config[] = {
106  {
107  .dev = TIM3,
108  .rcc_mask = RCC_APB1ENR_TIM3EN,
109  .chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0 },
110  { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1 },
111  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
112  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
113  .af = GPIO_AF2,
114  .bus = APB1
115  }
116 };
117 
118 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
119 
128 static const uint8_t spi_divtable[2][5] = {
129  { /* for APB1 @ 36000000Hz */
130  7, /* -> 140625Hz */
131  6, /* -> 281250Hz */
132  4, /* -> 1125000Hz */
133  2, /* -> 4500000Hz */
134  1 /* -> 9000000Hz */
135  },
136  { /* for APB2 @ 72000000Hz */
137  7, /* -> 281250Hz */
138  7, /* -> 281250Hz */
139  5, /* -> 1125000Hz */
140  3, /* -> 4500000Hz */
141  2 /* -> 9000000Hz */
142  }
143 };
144 
145 static const spi_conf_t spi_config[] = {
146  {
147  .dev = SPI1,
148  .mosi_pin = GPIO_PIN(PORT_A, 7),
149  .miso_pin = GPIO_PIN(PORT_A, 6),
150  .sclk_pin = GPIO_PIN(PORT_A, 5),
151  .cs_pin = GPIO_UNDEF,
152  .af = GPIO_AF5,
153  .rccmask = RCC_APB2ENR_SPI1EN,
154  .apbbus = APB2
155  }
156 };
157 
158 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
159 
161 #ifdef __cplusplus
162 }
163 #endif
164 
165 #endif /* PERIPH_CONF_H */
166 
use alternate function 7
void * dev
UART, USART or LEUART device used.
TIMER_TypeDef * dev
TIMER device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
PWM device configuration.
NRF_TIMER_Type * dev
timer device
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define custom value to speficy undefined or unused GPIOs.
SPI module configuration options.
Timer configuration.
use alternate function 2
cc2538_ssi_t * dev
SSI device.