boards/nucleo-f334/include/periph_conf.h
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1 /*
2  * Copyright (C) 2015 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
20 #ifndef PERIPH_CONF_H
21 #define PERIPH_CONF_H
22 
23 #include "periph_cpu.h"
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
33 #define CLOCK_HSE (8000000U) /* external oscillator */
34 #define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
35 
36 /* the actual PLL values are automatically generated */
37 #define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE)
38 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
39 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
40 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
41 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
42 
43 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
44 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
45 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
46 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
47 
53 static const timer_conf_t timer_config[] = {
54  {
55  .dev = TIM2,
56  .max = 0xffffffff,
57  .rcc_mask = RCC_APB1ENR_TIM2EN,
58  .bus = APB1,
59  .irqn = TIM2_IRQn
60  }
61 };
62 
63 #define TIMER_0_ISR (isr_tim2)
64 
65 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
66 
72 static const uart_conf_t uart_config[] = {
73  {
74  .dev = USART2,
75  .rcc_mask = RCC_APB1ENR_USART2EN,
76  .rx_pin = GPIO_PIN(PORT_A, 3),
77  .tx_pin = GPIO_PIN(PORT_A, 2),
78  .rx_af = GPIO_AF7,
79  .tx_af = GPIO_AF7,
80  .bus = APB1,
81  .irqn = USART2_IRQn
82  }
83 };
84 
85 #define UART_0_ISR (isr_usart2)
86 
87 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
88 
94 static const pwm_conf_t pwm_config[] = {
95  {
96  .dev = TIM3,
97  .rcc_mask = RCC_APB1ENR_TIM3EN,
98  .chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0 },
99  { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1 },
100  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
101  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
102  .af = GPIO_AF2,
103  .bus = APB1
104  }
105 };
106 
107 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
108 
117 static const uint8_t spi_divtable[2][5] = {
118  { /* for APB1 @ 36000000Hz */
119  7, /* -> 140625Hz */
120  6, /* -> 281250Hz */
121  4, /* -> 1125000Hz */
122  2, /* -> 4500000Hz */
123  1 /* -> 9000000Hz */
124  },
125  { /* for APB2 @ 72000000Hz */
126  7, /* -> 281250Hz */
127  7, /* -> 281250Hz */
128  5, /* -> 1125000Hz */
129  3, /* -> 4500000Hz */
130  2 /* -> 9000000Hz */
131  }
132 };
133 
134 static const spi_conf_t spi_config[] = {
135  {
136  .dev = SPI1,
137  .mosi_pin = GPIO_PIN(PORT_A, 7),
138  .miso_pin = GPIO_PIN(PORT_A, 6),
139  .sclk_pin = GPIO_PIN(PORT_A, 5),
140  .cs_pin = GPIO_UNDEF,
141  .af = GPIO_AF5,
142  .rccmask = RCC_APB2ENR_SPI1EN,
143  .apbbus = APB2
144  }
145 };
146 
147 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
148 
150 #ifdef __cplusplus
151 }
152 #endif
153 
154 #endif /* PERIPH_CONF_H */
155 
use alternate function 7
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
PWM configuration structure.
LPC_CTxxBx_Type * dev
PWM device.
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
use alternate function 2
cc2538_ssi_t * dev
SSI device.