boards/nucleo-f334/include/periph_conf.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2015 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
20 #ifndef PERIPH_CONF_H
21 #define PERIPH_CONF_H
22 
23 #include "periph_cpu.h"
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
36 /* give the target core clock (HCLK) frequency [in Hz],
37  * maximum: 72MHz */
38 #define CLOCK_CORECLOCK (72000000U)
39 /* 0: no external high speed crystal available
40  * else: actual crystal frequency [in Hz] */
41 #define CLOCK_HSE (8000000U)
42 /* 0: no external low speed crystal available,
43  * 1: external crystal available (always 32.768kHz) */
44 #define CLOCK_LSE (1)
45 /* peripheral clock setup */
46 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
47 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
48 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
49 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
50 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
51 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
52 
53 /* PLL factors */
54 #define CLOCK_PLL_PREDIV (1)
55 #define CLOCK_PLL_MUL (9)
56 
62 static const timer_conf_t timer_config[] = {
63  {
64  .dev = TIM2,
65  .max = 0xffffffff,
66  .rcc_mask = RCC_APB1ENR_TIM2EN,
67  .bus = APB1,
68  .irqn = TIM2_IRQn
69  }
70 };
71 
72 #define TIMER_0_ISR (isr_tim2)
73 
74 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
75 
81 static const uart_conf_t uart_config[] = {
82  {
83  .dev = USART2,
84  .rcc_mask = RCC_APB1ENR_USART2EN,
85  .rx_pin = GPIO_PIN(PORT_A, 3),
86  .tx_pin = GPIO_PIN(PORT_A, 2),
87  .rx_af = GPIO_AF7,
88  .tx_af = GPIO_AF7,
89  .bus = APB1,
90  .irqn = USART2_IRQn
91  }
92 };
93 
94 #define UART_0_ISR (isr_usart2)
95 
96 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
97 
103 static const pwm_conf_t pwm_config[] = {
104  {
105  .dev = TIM3,
106  .rcc_mask = RCC_APB1ENR_TIM3EN,
107  .chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0 },
108  { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1 },
109  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
110  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
111  .af = GPIO_AF2,
112  .bus = APB1
113  }
114 };
115 
116 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
117 
126 static const uint8_t spi_divtable[2][5] = {
127  { /* for APB1 @ 36000000Hz */
128  7, /* -> 140625Hz */
129  6, /* -> 281250Hz */
130  4, /* -> 1125000Hz */
131  2, /* -> 4500000Hz */
132  1 /* -> 9000000Hz */
133  },
134  { /* for APB2 @ 72000000Hz */
135  7, /* -> 281250Hz */
136  7, /* -> 281250Hz */
137  5, /* -> 1125000Hz */
138  3, /* -> 4500000Hz */
139  2 /* -> 9000000Hz */
140  }
141 };
142 
143 static const spi_conf_t spi_config[] = {
144  {
145  .dev = SPI1,
146  .mosi_pin = GPIO_PIN(PORT_A, 7),
147  .miso_pin = GPIO_PIN(PORT_A, 6),
148  .sclk_pin = GPIO_PIN(PORT_A, 5),
149  .cs_pin = GPIO_UNDEF,
150  .af = GPIO_AF5,
151  .rccmask = RCC_APB2ENR_SPI1EN,
152  .apbbus = APB2
153  }
154 };
155 
156 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
157 
159 #ifdef __cplusplus
160 }
161 #endif
162 
163 #endif /* PERIPH_CONF_H */
164 
use alternate function 7
void * dev
UART, USART or LEUART device used.
TIMER_TypeDef * dev
TIMER device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
PWM device configuration.
NRF_TIMER_Type * dev
timer device
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define custom value to speficy undefined or unused GPIOs.
SPI module configuration options.
Timer configuration.
use alternate function 2
cc2538_ssi_t * dev
SSI device.