boards/nucleo-f334/include/periph_conf.h
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1 /*
2  * Copyright (C) 2015 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
20 #ifndef PERIPH_CONF_H
21 #define PERIPH_CONF_H
22 
23 #include "periph_cpu.h"
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
33 #define CLOCK_HSE (8000000U) /* external oscillator */
34 #define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
35 
36 /* the actual PLL values are automatically generated */
37 #define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE)
38 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
39 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
40 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
41 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
42 
43 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
44 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
45 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
46 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
47 
53 #define DAC_NUMOF (0)
54 
60 #define DAC_NUMOF (0)
61 
67 static const timer_conf_t timer_config[] = {
68  {
69  .dev = TIM2,
70  .max = 0xffffffff,
71  .rcc_mask = RCC_APB1ENR_TIM2EN,
72  .bus = APB1,
73  .irqn = TIM2_IRQn
74  }
75 };
76 
77 #define TIMER_0_ISR (isr_tim2)
78 
79 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
80 
86 static const uart_conf_t uart_config[] = {
87  {
88  .dev = USART2,
89  .rcc_mask = RCC_APB1ENR_USART2EN,
90  .rx_pin = GPIO_PIN(PORT_A, 3),
91  .tx_pin = GPIO_PIN(PORT_A, 2),
92  .rx_af = GPIO_AF7,
93  .tx_af = GPIO_AF7,
94  .bus = APB1,
95  .irqn = USART2_IRQn
96  }
97 };
98 
99 #define UART_0_ISR (isr_usart2)
100 
101 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
102 
108 static const pwm_conf_t pwm_config[] = {
109  {
110  .dev = TIM3,
111  .rcc_mask = RCC_APB1ENR_TIM3EN,
112  .chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0 },
113  { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1 },
114  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
115  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
116  .af = GPIO_AF2,
117  .bus = APB1
118  }
119 };
120 
121 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
122 
131 static const uint8_t spi_divtable[2][5] = {
132  { /* for APB1 @ 36000000Hz */
133  7, /* -> 140625Hz */
134  6, /* -> 281250Hz */
135  4, /* -> 1125000Hz */
136  2, /* -> 4500000Hz */
137  1 /* -> 9000000Hz */
138  },
139  { /* for APB2 @ 72000000Hz */
140  7, /* -> 281250Hz */
141  7, /* -> 281250Hz */
142  5, /* -> 1125000Hz */
143  3, /* -> 4500000Hz */
144  2 /* -> 9000000Hz */
145  }
146 };
147 
148 static const spi_conf_t spi_config[] = {
149  {
150  .dev = SPI1,
151  .mosi_pin = GPIO_PIN(PORT_A, 7),
152  .miso_pin = GPIO_PIN(PORT_A, 6),
153  .sclk_pin = GPIO_PIN(PORT_A, 5),
154  .cs_pin = GPIO_UNDEF,
155  .af = GPIO_AF5,
156  .rccmask = RCC_APB2ENR_SPI1EN,
157  .apbbus = APB2
158  }
159 };
160 
161 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
162 
164 #ifdef __cplusplus
165 }
166 #endif
167 
168 #endif /* PERIPH_CONF_H */
169 
use alternate function 7
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
PWM configuration structure.
LPC_CTxxBx_Type * dev
PWM device.
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
use alternate function 2
cc2538_ssi_t * dev
SSI device.