boards/nucleo-f303/include/periph_conf.h
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1 /*
2  * Copyright (C) 2015 Freie Universit├Ąt Berlin
3  * Copyright (C) 2015 Hamburg University of Applied Sciences
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 #include "periph_cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
34 #define CLOCK_HSE (8000000U) /* external oscillator */
35 #define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
36 
37 /* the actual PLL values are automatically generated */
38 #define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE)
39 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
40 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
41 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
42 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
43 
44 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
45 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
46 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
47 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
48 
54 static const timer_conf_t timer_config[] = {
55  {
56  .dev = TIM2,
57  .max = 0xffffffff,
58  .rcc_mask = RCC_APB1ENR_TIM2EN,
59  .bus = APB1,
60  .irqn = TIM2_IRQn
61  }
62 };
63 
64 #define TIMER_0_ISR isr_tim2
65 
66 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
67 
73 static const uart_conf_t uart_config[] = {
74  {
75  .dev = USART2,
76  .rcc_mask = RCC_APB1ENR_USART2EN,
77  .rx_pin = GPIO_PIN(PORT_A, 3),
78  .tx_pin = GPIO_PIN(PORT_A, 2),
79  .rx_af = GPIO_AF7,
80  .tx_af = GPIO_AF7,
81  .bus = APB1,
82  .irqn = USART2_IRQn
83  },
84  {
85  .dev = USART1,
86  .rcc_mask = RCC_APB2ENR_USART1EN,
87  .rx_pin = GPIO_PIN(PORT_A, 10),
88  .tx_pin = GPIO_PIN(PORT_A, 9),
89  .rx_af = GPIO_AF7,
90  .tx_af = GPIO_AF7,
91  .bus = APB2,
92  .irqn = USART1_IRQn
93  },
94  {
95  .dev = USART3,
96  .rcc_mask = RCC_APB1ENR_USART3EN,
97  .rx_pin = GPIO_PIN(PORT_B, 11),
98  .tx_pin = GPIO_PIN(PORT_B, 10),
99  .rx_af = GPIO_AF7,
100  .tx_af = GPIO_AF7,
101  .bus = APB1,
102  .irqn = USART3_IRQn
103  }
104 };
105 
106 #define UART_0_ISR (isr_usart2)
107 #define UART_1_ISR (isr_usart1)
108 #define UART_2_ISR (isr_usart3)
109 
110 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
111 
117 static const pwm_conf_t pwm_config[] = {
118  {
119  .dev = TIM3,
120  .rcc_mask = RCC_APB1ENR_TIM3EN,
121  .chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0 },
122  { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1 },
123  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
124  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
125  .af = GPIO_AF2,
126  .bus = APB1
127  }
128 };
129 
130 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
131 
140 static const uint8_t spi_divtable[2][5] = {
141  { /* for APB1 @ 36000000Hz */
142  7, /* -> 140625Hz */
143  6, /* -> 281250Hz */
144  4, /* -> 1125000Hz */
145  2, /* -> 4500000Hz */
146  1 /* -> 9000000Hz */
147  },
148  { /* for APB2 @ 72000000Hz */
149  7, /* -> 281250Hz */
150  7, /* -> 281250Hz */
151  5, /* -> 1125000Hz */
152  3, /* -> 4500000Hz */
153  2 /* -> 9000000Hz */
154  }
155 };
156 
157 static const spi_conf_t spi_config[] = {
158  {
159  .dev = SPI1,
160  .mosi_pin = GPIO_PIN(PORT_A, 7),
161  .miso_pin = GPIO_PIN(PORT_A, 6),
162  .sclk_pin = GPIO_PIN(PORT_A, 5),
163  .cs_pin = GPIO_PIN(PORT_A, 4),
164  .af = GPIO_AF5,
165  .rccmask = RCC_APB2ENR_SPI1EN,
166  .apbbus = APB2
167  },
168  {
169  .dev = SPI1,
170  .mosi_pin = GPIO_PIN(PORT_C, 12),
171  .miso_pin = GPIO_PIN(PORT_C, 11),
172  .sclk_pin = GPIO_PIN(PORT_C, 10),
173  .cs_pin = GPIO_UNDEF,
174  .af = GPIO_AF6,
175  .rccmask = RCC_APB1ENR_SPI3EN,
176  .apbbus = APB1
177  }
178 };
179 
180 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
181 
187 #define I2C_NUMOF (2U)
188 #define I2C_0_EN 1
189 #define I2C_1_EN 1
190 #define I2C_IRQ_PRIO 1
191 #define I2C_APBCLK (CLOCK_APB1)
192 
193 /* I2C 0 device configuration */
194 #define I2C_0_DEV I2C1
195 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
196 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
197 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
198 #define I2C_0_EVT_ISR isr_i2c1_ev
199 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
200 #define I2C_0_ERR_ISR isr_i2c1_er
201 /* I2C 0 pin configuration */
202 #define I2C_0_SCL_PORT GPIOB
203 #define I2C_0_SCL_PIN 8
204 #define I2C_0_SCL_AF 4
205 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
206 #define I2C_0_SDA_PORT GPIOB
207 #define I2C_0_SDA_PIN 9
208 #define I2C_0_SDA_AF 4
209 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
210 
211 /* I2C 1 device configuration */
212 #define I2C_1_DEV I2C3
213 #define I2C_1_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C3EN))
214 #define I2C_1_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C3EN))
215 #define I2C_1_EVT_IRQ I2C3_EV_IRQn
216 #define I2C_1_EVT_ISR isr_i2c3_ev
217 #define I2C_1_ERR_IRQ I2C3_ER_IRQn
218 #define I2C_1_ERR_ISR isr_i2c3_er
219 /* I2C 1 pin configuration */
220 #define I2C_1_SCL_PORT GPIOA
221 #define I2C_1_SCL_PIN 8
222 #define I2C_1_SCL_AF 3
223 #define I2C_1_SCL_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOAEN))
224 #define I2C_1_SDA_PORT GPIOB
225 #define I2C_1_SDA_PIN 5
226 #define I2C_1_SDA_AF 8
227 #define I2C_1_SDA_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
228 
230 #ifdef __cplusplus
231 }
232 #endif
233 
234 #endif /* PERIPH_CONF_H */
use alternate function 7
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 6
PWM configuration structure.
LPC_CTxxBx_Type * dev
PWM device.
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI module configuration options.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
use alternate function 2
cc2538_ssi_t * dev
SSI device.