boards/nucleo-f303/include/periph_conf.h
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1 /*
2  * Copyright (C) 2015 Freie Universit├Ąt Berlin
3  * Copyright (C) 2015 Hamburg University of Applied Sciences
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
23 #ifndef PERIPH_CONF_H
24 #define PERIPH_CONF_H
25 
26 #include "periph_cpu.h"
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
39 /* give the target core clock (HCLK) frequency [in Hz],
40  * maximum: 72MHz */
41 #define CLOCK_CORECLOCK (72000000U)
42 /* 0: no external high speed crystal available
43  * else: actual crystal frequency [in Hz] */
44 #define CLOCK_HSE (8000000U)
45 /* 0: no external low speed crystal available,
46  * 1: external crystal available (always 32.768kHz) */
47 #define CLOCK_LSE (1)
48 /* peripheral clock setup */
49 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
50 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
51 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
52 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
53 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
54 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
55 
56 /* PLL factors */
57 #define CLOCK_PLL_PREDIV (1)
58 #define CLOCK_PLL_MUL (9)
59 
65 static const timer_conf_t timer_config[] = {
66  {
67  .dev = TIM2,
68  .max = 0xffffffff,
69  .rcc_mask = RCC_APB1ENR_TIM2EN,
70  .bus = APB1,
71  .irqn = TIM2_IRQn
72  }
73 };
74 
75 #define TIMER_0_ISR isr_tim2
76 
77 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
78 
84 static const uart_conf_t uart_config[] = {
85  {
86  .dev = USART2,
87  .rcc_mask = RCC_APB1ENR_USART2EN,
88  .rx_pin = GPIO_PIN(PORT_A, 3),
89  .tx_pin = GPIO_PIN(PORT_A, 2),
90  .rx_af = GPIO_AF7,
91  .tx_af = GPIO_AF7,
92  .bus = APB1,
93  .irqn = USART2_IRQn
94  },
95  {
96  .dev = USART1,
97  .rcc_mask = RCC_APB2ENR_USART1EN,
98  .rx_pin = GPIO_PIN(PORT_A, 10),
99  .tx_pin = GPIO_PIN(PORT_A, 9),
100  .rx_af = GPIO_AF7,
101  .tx_af = GPIO_AF7,
102  .bus = APB2,
103  .irqn = USART1_IRQn
104  },
105  {
106  .dev = USART3,
107  .rcc_mask = RCC_APB1ENR_USART3EN,
108  .rx_pin = GPIO_PIN(PORT_B, 11),
109  .tx_pin = GPIO_PIN(PORT_B, 10),
110  .rx_af = GPIO_AF7,
111  .tx_af = GPIO_AF7,
112  .bus = APB1,
113  .irqn = USART3_IRQn
114  }
115 };
116 
117 #define UART_0_ISR (isr_usart2)
118 #define UART_1_ISR (isr_usart1)
119 #define UART_2_ISR (isr_usart3)
120 
121 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
122 
128 static const pwm_conf_t pwm_config[] = {
129  {
130  .dev = TIM3,
131  .rcc_mask = RCC_APB1ENR_TIM3EN,
132  .chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0 },
133  { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1 },
134  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
135  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
136  .af = GPIO_AF2,
137  .bus = APB1
138  }
139 };
140 
141 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
142 
151 static const uint8_t spi_divtable[2][5] = {
152  { /* for APB1 @ 36000000Hz */
153  7, /* -> 140625Hz */
154  6, /* -> 281250Hz */
155  4, /* -> 1125000Hz */
156  2, /* -> 4500000Hz */
157  1 /* -> 9000000Hz */
158  },
159  { /* for APB2 @ 72000000Hz */
160  7, /* -> 281250Hz */
161  7, /* -> 281250Hz */
162  5, /* -> 1125000Hz */
163  3, /* -> 4500000Hz */
164  2 /* -> 9000000Hz */
165  }
166 };
167 
168 static const spi_conf_t spi_config[] = {
169  {
170  .dev = SPI1,
171  .mosi_pin = GPIO_PIN(PORT_A, 7),
172  .miso_pin = GPIO_PIN(PORT_A, 6),
173  .sclk_pin = GPIO_PIN(PORT_A, 5),
174  .cs_pin = GPIO_PIN(PORT_A, 4),
175  .af = GPIO_AF5,
176  .rccmask = RCC_APB2ENR_SPI1EN,
177  .apbbus = APB2
178  },
179  {
180  .dev = SPI1,
181  .mosi_pin = GPIO_PIN(PORT_C, 12),
182  .miso_pin = GPIO_PIN(PORT_C, 11),
183  .sclk_pin = GPIO_PIN(PORT_C, 10),
184  .cs_pin = GPIO_UNDEF,
185  .af = GPIO_AF6,
186  .rccmask = RCC_APB1ENR_SPI3EN,
187  .apbbus = APB1
188  }
189 };
190 
191 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
192 
198 #define I2C_NUMOF (2U)
199 #define I2C_0_EN 1
200 #define I2C_1_EN 1
201 #define I2C_IRQ_PRIO 1
202 #define I2C_APBCLK (CLOCK_APB1)
203 
204 /* I2C 0 device configuration */
205 #define I2C_0_DEV I2C1
206 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
207 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
208 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
209 #define I2C_0_EVT_ISR isr_i2c1_ev
210 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
211 #define I2C_0_ERR_ISR isr_i2c1_er
212 /* I2C 0 pin configuration */
213 #define I2C_0_SCL_PORT GPIOB
214 #define I2C_0_SCL_PIN 8
215 #define I2C_0_SCL_AF 4
216 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
217 #define I2C_0_SDA_PORT GPIOB
218 #define I2C_0_SDA_PIN 9
219 #define I2C_0_SDA_AF 4
220 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
221 
222 /* I2C 1 device configuration */
223 #define I2C_1_DEV I2C3
224 #define I2C_1_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C3EN))
225 #define I2C_1_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C3EN))
226 #define I2C_1_EVT_IRQ I2C3_EV_IRQn
227 #define I2C_1_EVT_ISR isr_i2c3_ev
228 #define I2C_1_ERR_IRQ I2C3_ER_IRQn
229 #define I2C_1_ERR_ISR isr_i2c3_er
230 /* I2C 1 pin configuration */
231 #define I2C_1_SCL_PORT GPIOA
232 #define I2C_1_SCL_PIN 8
233 #define I2C_1_SCL_AF 3
234 #define I2C_1_SCL_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOAEN))
235 #define I2C_1_SDA_PORT GPIOB
236 #define I2C_1_SDA_PIN 5
237 #define I2C_1_SDA_AF 8
238 #define I2C_1_SDA_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
239 
241 #ifdef __cplusplus
242 }
243 #endif
244 
245 #endif /* PERIPH_CONF_H */
246 
use alternate function 7
void * dev
UART, USART or LEUART device used.
TIMER_TypeDef * dev
TIMER device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 6
PWM device configuration.
NRF_TIMER_Type * dev
timer device
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define custom value to speficy undefined or unused GPIOs.
SPI module configuration options.
Timer configuration.
use alternate function 2
cc2538_ssi_t * dev
SSI device.