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boards/nucleo-f303/include/periph_conf.h
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1 /*
2  * Copyright (C) 2015 Freie Universit├Ąt Berlin
3  * Copyright (C) 2015 Hamburg University of Applied Sciences
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 #include "periph_cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
34 #define CLOCK_HSE (8000000U) /* external oscillator */
35 #define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
36 
37 /* the actual PLL values are automatically generated */
38 #define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE)
39 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
40 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
41 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
42 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
43 
44 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
45 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
46 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
47 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
48 
54 #define DAC_NUMOF (0)
55 
61 static const timer_conf_t timer_config[] = {
62  {
63  .dev = TIM2,
64  .max = 0xffffffff,
65  .rcc_mask = RCC_APB1ENR_TIM2EN,
66  .bus = APB1,
67  .irqn = TIM2_IRQn
68  }
69 };
70 
71 #define TIMER_0_ISR isr_tim2
72 
73 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
74 
80 static const uart_conf_t uart_config[] = {
81  {
82  .dev = USART2,
83  .rcc_mask = RCC_APB1ENR_USART2EN,
84  .rx_pin = GPIO_PIN(PORT_A, 3),
85  .tx_pin = GPIO_PIN(PORT_A, 2),
86  .rx_af = GPIO_AF7,
87  .tx_af = GPIO_AF7,
88  .bus = APB1,
89  .irqn = USART2_IRQn
90  },
91  {
92  .dev = USART1,
93  .rcc_mask = RCC_APB2ENR_USART1EN,
94  .rx_pin = GPIO_PIN(PORT_A, 10),
95  .tx_pin = GPIO_PIN(PORT_A, 9),
96  .rx_af = GPIO_AF7,
97  .tx_af = GPIO_AF7,
98  .bus = APB2,
99  .irqn = USART1_IRQn
100  },
101  {
102  .dev = USART3,
103  .rcc_mask = RCC_APB1ENR_USART3EN,
104  .rx_pin = GPIO_PIN(PORT_B, 11),
105  .tx_pin = GPIO_PIN(PORT_B, 10),
106  .rx_af = GPIO_AF7,
107  .tx_af = GPIO_AF7,
108  .bus = APB1,
109  .irqn = USART3_IRQn
110  }
111 };
112 
113 #define UART_0_ISR (isr_usart2)
114 #define UART_1_ISR (isr_usart1)
115 #define UART_2_ISR (isr_usart3)
116 
117 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
118 
124 static const pwm_conf_t pwm_config[] = {
125  {
126  .dev = TIM3,
127  .rcc_mask = RCC_APB1ENR_TIM3EN,
128  .chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0 },
129  { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1 },
130  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
131  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
132  .af = GPIO_AF2,
133  .bus = APB1
134  }
135 };
136 
137 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
138 
147 static const uint8_t spi_divtable[2][5] = {
148  { /* for APB1 @ 36000000Hz */
149  7, /* -> 140625Hz */
150  6, /* -> 281250Hz */
151  4, /* -> 1125000Hz */
152  2, /* -> 4500000Hz */
153  1 /* -> 9000000Hz */
154  },
155  { /* for APB2 @ 72000000Hz */
156  7, /* -> 281250Hz */
157  7, /* -> 281250Hz */
158  5, /* -> 1125000Hz */
159  3, /* -> 4500000Hz */
160  2 /* -> 9000000Hz */
161  }
162 };
163 
164 static const spi_conf_t spi_config[] = {
165  {
166  .dev = SPI1,
167  .mosi_pin = GPIO_PIN(PORT_A, 7),
168  .miso_pin = GPIO_PIN(PORT_A, 6),
169  .sclk_pin = GPIO_PIN(PORT_A, 5),
170  .cs_pin = GPIO_PIN(PORT_A, 4),
171  .af = GPIO_AF5,
172  .rccmask = RCC_APB2ENR_SPI1EN,
173  .apbbus = APB2
174  },
175  {
176  .dev = SPI1,
177  .mosi_pin = GPIO_PIN(PORT_C, 12),
178  .miso_pin = GPIO_PIN(PORT_C, 11),
179  .sclk_pin = GPIO_PIN(PORT_C, 10),
180  .cs_pin = GPIO_UNDEF,
181  .af = GPIO_AF6,
182  .rccmask = RCC_APB1ENR_SPI3EN,
183  .apbbus = APB1
184  }
185 };
186 
187 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
188 
194 #define I2C_NUMOF (2U)
195 #define I2C_0_EN 1
196 #define I2C_1_EN 1
197 #define I2C_IRQ_PRIO 1
198 #define I2C_APBCLK (36000000U)
199 
200 /* I2C 0 device configuration */
201 #define I2C_0_DEV I2C1
202 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
203 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
204 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
205 #define I2C_0_EVT_ISR isr_i2c1_ev
206 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
207 #define I2C_0_ERR_ISR isr_i2c1_er
208 /* I2C 0 pin configuration */
209 #define I2C_0_SCL_PORT GPIOB
210 #define I2C_0_SCL_PIN 8
211 #define I2C_0_SCL_AF 4
212 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
213 #define I2C_0_SDA_PORT GPIOB
214 #define I2C_0_SDA_PIN 9
215 #define I2C_0_SDA_AF 4
216 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
217 
218 /* I2C 1 device configuration */
219 #define I2C_1_DEV I2C3
220 #define I2C_1_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C3EN))
221 #define I2C_1_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C3EN))
222 #define I2C_1_EVT_IRQ I2C3_EV_IRQn
223 #define I2C_1_EVT_ISR isr_i2c3_ev
224 #define I2C_1_ERR_IRQ I2C3_ER_IRQn
225 #define I2C_1_ERR_ISR isr_i2c3_er
226 /* I2C 1 pin configuration */
227 #define I2C_1_SCL_PORT GPIOA
228 #define I2C_1_SCL_PIN 8
229 #define I2C_1_SCL_AF 3
230 #define I2C_1_SCL_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOAEN))
231 #define I2C_1_SDA_PORT GPIOB
232 #define I2C_1_SDA_PIN 5
233 #define I2C_1_SDA_AF 8
234 #define I2C_1_SDA_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
235 
237 #ifdef __cplusplus
238 }
239 #endif
240 
241 #endif /* PERIPH_CONF_H */
use alternate function 7
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 6
PWM configuration structure.
LPC_CTxxBx_Type * dev
PWM device.
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
use alternate function 2
cc2538_ssi_t * dev
SSI device.