boards/nucleo-f303/include/periph_conf.h
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1 /*
2  * Copyright (C) 2015 Freie Universit├Ąt Berlin
3  * Copyright (C) 2015 Hamburg University of Applied Sciences
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 #include "periph_cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
37 /* give the target core clock (HCLK) frequency [in Hz],
38  * maximum: 72MHz */
39 #define CLOCK_CORECLOCK (72000000U)
40 /* 0: no external high speed crystal available
41  * else: actual crystal frequency [in Hz] */
42 #define CLOCK_HSE (8000000U)
43 /* 0: no external low speed crystal available,
44  * 1: external crystal available (always 32.768kHz) */
45 #define CLOCK_LSE (1)
46 /* peripheral clock setup */
47 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
48 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
49 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
50 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
51 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
52 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
53 
54 /* PLL factors */
55 #define CLOCK_PLL_PREDIV (1)
56 #define CLOCK_PLL_MUL (9)
57 
63 static const timer_conf_t timer_config[] = {
64  {
65  .dev = TIM2,
66  .max = 0xffffffff,
67  .rcc_mask = RCC_APB1ENR_TIM2EN,
68  .bus = APB1,
69  .irqn = TIM2_IRQn
70  }
71 };
72 
73 #define TIMER_0_ISR isr_tim2
74 
75 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
76 
82 static const uart_conf_t uart_config[] = {
83  {
84  .dev = USART2,
85  .rcc_mask = RCC_APB1ENR_USART2EN,
86  .rx_pin = GPIO_PIN(PORT_A, 3),
87  .tx_pin = GPIO_PIN(PORT_A, 2),
88  .rx_af = GPIO_AF7,
89  .tx_af = GPIO_AF7,
90  .bus = APB1,
91  .irqn = USART2_IRQn
92  },
93  {
94  .dev = USART1,
95  .rcc_mask = RCC_APB2ENR_USART1EN,
96  .rx_pin = GPIO_PIN(PORT_A, 10),
97  .tx_pin = GPIO_PIN(PORT_A, 9),
98  .rx_af = GPIO_AF7,
99  .tx_af = GPIO_AF7,
100  .bus = APB2,
101  .irqn = USART1_IRQn
102  },
103  {
104  .dev = USART3,
105  .rcc_mask = RCC_APB1ENR_USART3EN,
106  .rx_pin = GPIO_PIN(PORT_B, 11),
107  .tx_pin = GPIO_PIN(PORT_B, 10),
108  .rx_af = GPIO_AF7,
109  .tx_af = GPIO_AF7,
110  .bus = APB1,
111  .irqn = USART3_IRQn
112  }
113 };
114 
115 #define UART_0_ISR (isr_usart2)
116 #define UART_1_ISR (isr_usart1)
117 #define UART_2_ISR (isr_usart3)
118 
119 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
120 
126 static const pwm_conf_t pwm_config[] = {
127  {
128  .dev = TIM3,
129  .rcc_mask = RCC_APB1ENR_TIM3EN,
130  .chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0 },
131  { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1 },
132  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
133  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
134  .af = GPIO_AF2,
135  .bus = APB1
136  }
137 };
138 
139 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
140 
149 static const uint8_t spi_divtable[2][5] = {
150  { /* for APB1 @ 36000000Hz */
151  7, /* -> 140625Hz */
152  6, /* -> 281250Hz */
153  4, /* -> 1125000Hz */
154  2, /* -> 4500000Hz */
155  1 /* -> 9000000Hz */
156  },
157  { /* for APB2 @ 72000000Hz */
158  7, /* -> 281250Hz */
159  7, /* -> 281250Hz */
160  5, /* -> 1125000Hz */
161  3, /* -> 4500000Hz */
162  2 /* -> 9000000Hz */
163  }
164 };
165 
166 static const spi_conf_t spi_config[] = {
167  {
168  .dev = SPI1,
169  .mosi_pin = GPIO_PIN(PORT_A, 7),
170  .miso_pin = GPIO_PIN(PORT_A, 6),
171  .sclk_pin = GPIO_PIN(PORT_A, 5),
172  .cs_pin = GPIO_PIN(PORT_A, 4),
173  .af = GPIO_AF5,
174  .rccmask = RCC_APB2ENR_SPI1EN,
175  .apbbus = APB2
176  },
177  {
178  .dev = SPI1,
179  .mosi_pin = GPIO_PIN(PORT_C, 12),
180  .miso_pin = GPIO_PIN(PORT_C, 11),
181  .sclk_pin = GPIO_PIN(PORT_C, 10),
182  .cs_pin = GPIO_UNDEF,
183  .af = GPIO_AF6,
184  .rccmask = RCC_APB1ENR_SPI3EN,
185  .apbbus = APB1
186  }
187 };
188 
189 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
190 
196 #define I2C_NUMOF (2U)
197 #define I2C_0_EN 1
198 #define I2C_1_EN 1
199 #define I2C_IRQ_PRIO 1
200 #define I2C_APBCLK (CLOCK_APB1)
201 
202 /* I2C 0 device configuration */
203 #define I2C_0_DEV I2C1
204 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
205 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
206 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
207 #define I2C_0_EVT_ISR isr_i2c1_ev
208 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
209 #define I2C_0_ERR_ISR isr_i2c1_er
210 /* I2C 0 pin configuration */
211 #define I2C_0_SCL_PORT GPIOB
212 #define I2C_0_SCL_PIN 8
213 #define I2C_0_SCL_AF 4
214 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
215 #define I2C_0_SDA_PORT GPIOB
216 #define I2C_0_SDA_PIN 9
217 #define I2C_0_SDA_AF 4
218 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
219 
220 /* I2C 1 device configuration */
221 #define I2C_1_DEV I2C3
222 #define I2C_1_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C3EN))
223 #define I2C_1_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C3EN))
224 #define I2C_1_EVT_IRQ I2C3_EV_IRQn
225 #define I2C_1_EVT_ISR isr_i2c3_ev
226 #define I2C_1_ERR_IRQ I2C3_ER_IRQn
227 #define I2C_1_ERR_ISR isr_i2c3_er
228 /* I2C 1 pin configuration */
229 #define I2C_1_SCL_PORT GPIOA
230 #define I2C_1_SCL_PIN 8
231 #define I2C_1_SCL_AF 3
232 #define I2C_1_SCL_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOAEN))
233 #define I2C_1_SDA_PORT GPIOB
234 #define I2C_1_SDA_PIN 5
235 #define I2C_1_SDA_AF 8
236 #define I2C_1_SDA_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
237 
239 #ifdef __cplusplus
240 }
241 #endif
242 
243 #endif /* PERIPH_CONF_H */
use alternate function 7
void * dev
UART, USART or LEUART device used.
TIMER_TypeDef * dev
TIMER device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 6
PWM device configuration.
NRF_TIMER_Type * dev
timer device
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define custom value to speficy undefined or unused GPIOs.
SPI module configuration options.
Timer configuration.
use alternate function 2
cc2538_ssi_t * dev
SSI device.