periph_conf.h File Reference

Peripheral MCU configuration for the nucleo-f302r8 board. More...

Detailed Description

#include "periph_cpu.h"
#include "cfg_timer_tim2.h"
+ Include dependency graph for periph_conf.h:

Go to the source code of this file.

Clock settings

Note
This is auto-generated from cpu/stm32_common/dist/clk_conf/clk_conf.c
#define CLOCK_CORECLOCK   (72000000U)
 
#define CLOCK_HSE   (8000000U)
 
#define CLOCK_LSE   (1)
 
#define CLOCK_AHB_DIV   RCC_CFGR_HPRE_DIV1
 
#define CLOCK_AHB   (CLOCK_CORECLOCK / 1)
 
#define CLOCK_APB1_DIV   RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
 
#define CLOCK_APB1   (CLOCK_CORECLOCK / 2)
 
#define CLOCK_APB2_DIV   RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
 
#define CLOCK_APB2   (CLOCK_CORECLOCK / 1)
 
#define CLOCK_PLL_PREDIV   (1)
 
#define CLOCK_PLL_MUL   (9)
 

UART configuration

#define UART_0_ISR   (isr_usart2)
 
#define UART_1_ISR   (isr_usart1)
 
#define UART_2_ISR   (isr_usart3)
 
#define UART_NUMOF   ARRAY_SIZE(uart_config)
 
static const uart_conf_t uart_config []
 

PWM configuration

#define PWM_NUMOF   ARRAY_SIZE(pwm_config)
 
static const pwm_conf_t pwm_config []
 

SPI configuration

Note
The spi_divtable is auto-generated from cpu/stm32_common/dist/spi_divtable/spi_divtable.c
#define SPI_NUMOF   ARRAY_SIZE(spi_config)
 
static const uint8_t spi_divtable [2][5]
 
static const spi_conf_t spi_config []
 

I2C configuration

#define I2C_0_ISR   isr_i2c1_er
 
#define I2C_1_ISR   isr_i2c3_er
 
#define I2C_NUMOF   ARRAY_SIZE(i2c_config)
 
static const i2c_conf_t i2c_config []
 

Variable Documentation

◆ i2c_config

const i2c_conf_t i2c_config[]
static
Initial value:
= {
{
.dev = I2C1,
.speed = I2C_SPEED_NORMAL,
.scl_pin = GPIO_PIN(PORT_B, 8),
.sda_pin = GPIO_PIN(PORT_B, 9),
.scl_af = GPIO_AF4,
.sda_af = GPIO_AF4,
.bus = APB1,
.rcc_mask = RCC_APB1ENR_I2C1EN,
.rcc_sw_mask = RCC_CFGR3_I2C1SW,
.irqn = I2C1_ER_IRQn
},
{
.dev = I2C3,
.speed = I2C_SPEED_NORMAL,
.scl_pin = GPIO_PIN(PORT_A, 8),
.sda_pin = GPIO_PIN(PORT_A, 5),
.scl_af = GPIO_AF5,
.sda_af = GPIO_AF8,
.bus = APB1,
.rcc_mask = RCC_APB1ENR_I2C3EN,
.rcc_sw_mask = RCC_CFGR3_I2C3SW,
.irqn = I2C3_ER_IRQn
}
}
use alternate function 4
use alternate function 8
APB1 bus.
port A
Definition: periph_cpu.h:36
use alternate function 5
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
normal mode: ~100kbit/s
Definition: periph_cpu.h:116
port B
Definition: periph_cpu.h:37

Definition at line 170 of file periph_conf.h.

◆ pwm_config

const pwm_conf_t pwm_config[]
static
Initial value:
= {
{
.dev = TIM16,
.rcc_mask = RCC_APB2ENR_TIM16EN,
.chan = { { .pin = GPIO_PIN(PORT_B, 4) , .cc_chan = 0 },
{ .pin = GPIO_UNDEF, .cc_chan = 0 },
{ .pin = GPIO_UNDEF, .cc_chan = 0 },
{ .pin = GPIO_UNDEF, .cc_chan = 0 } },
.af = GPIO_AF1,
.bus = APB2
}
}
use alternate function 1
APB2 bus.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
port B
Definition: periph_cpu.h:37

Definition at line 110 of file periph_conf.h.

◆ spi_config

const spi_conf_t spi_config[]
static
Initial value:
= {
{
.dev = SPI2,
.mosi_pin = GPIO_PIN(PORT_B, 15),
.miso_pin = GPIO_PIN(PORT_B, 14),
.sclk_pin = GPIO_PIN(PORT_B, 13),
.cs_pin = GPIO_PIN(PORT_B, 12),
.af = GPIO_AF5,
.rccmask = RCC_APB1ENR_SPI2EN,
.apbbus = APB1
}
}
APB1 bus.
use alternate function 5
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
port B
Definition: periph_cpu.h:37

Definition at line 150 of file periph_conf.h.

◆ spi_divtable

const uint8_t spi_divtable[2][5]
static
Initial value:
= {
{
7,
6,
4,
2,
1
},
{
7,
7,
5,
3,
2
}
}

Definition at line 133 of file periph_conf.h.