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boards/nucleo-f302/include/periph_conf.h
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1 /*
2  * Copyright (C) 2017 Inria
3  * Copyright (C) 2015 Freie Universit├Ąt Berlin
4  * Copyright (C) 2015 Hamburg University of Applied Sciences
5  *
6  * This file is subject to the terms and conditions of the GNU Lesser
7  * General Public License v2.1. See the file LICENSE in the top level
8  * directory for more details.
9  */
10 
23 #ifndef PERIPH_CONF_H
24 #define PERIPH_CONF_H
25 
26 #include "periph_cpu.h"
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
36 #define CLOCK_HSE (8000000U) /* external oscillator */
37 #define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
38 
39 /* the actual PLL values are automatically generated */
40 #define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE)
41 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
42 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
43 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
44 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
45 
46 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
47 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
48 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
49 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
50 
56 #define ADC_NUMOF (0)
57 
63 #define DAC_NUMOF (0)
64 
70 static const timer_conf_t timer_config[] = {
71  {
72  .dev = TIM2,
73  .max = 0xffffffff,
74  .rcc_mask = RCC_APB1ENR_TIM2EN,
75  .bus = APB1,
76  .irqn = TIM2_IRQn
77  }
78 };
79 
80 #define TIMER_0_ISR isr_tim2
81 
82 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
83 
89 static const uart_conf_t uart_config[] = {
90  {
91  .dev = USART2,
92  .rcc_mask = RCC_APB1ENR_USART2EN,
93  .rx_pin = GPIO_PIN(PORT_A, 3),
94  .tx_pin = GPIO_PIN(PORT_A, 2),
95  .rx_af = GPIO_AF7,
96  .tx_af = GPIO_AF7,
97  .bus = APB1,
98  .irqn = USART2_IRQn
99  },
100  {
101  .dev = USART1,
102  .rcc_mask = RCC_APB2ENR_USART1EN,
103  .rx_pin = GPIO_PIN(PORT_A, 10),
104  .tx_pin = GPIO_PIN(PORT_A, 9),
105  .rx_af = GPIO_AF7,
106  .tx_af = GPIO_AF7,
107  .bus = APB2,
108  .irqn = USART1_IRQn
109  },
110  {
111  .dev = USART3,
112  .rcc_mask = RCC_APB1ENR_USART3EN,
113  .rx_pin = GPIO_PIN(PORT_C, 11),
114  .tx_pin = GPIO_PIN(PORT_C, 10),
115  .rx_af = GPIO_AF7,
116  .tx_af = GPIO_AF7,
117  .bus = APB1,
118  .irqn = USART3_IRQn
119  }
120 };
121 
122 #define UART_0_ISR (isr_usart2)
123 #define UART_1_ISR (isr_usart1)
124 #define UART_2_ISR (isr_usart3)
125 
126 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
127 
133 static const pwm_conf_t pwm_config[] = {
134  {
135  .dev = TIM16,
136  .rcc_mask = RCC_APB2ENR_TIM16EN,
137  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
138  { .pin = GPIO_UNDEF, .cc_chan = 0 },
139  { .pin = GPIO_UNDEF, .cc_chan = 0 },
140  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
141  .af = GPIO_AF1,
142  .bus = APB2
143  }
144 };
145 
146 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
147 
156 static const uint8_t spi_divtable[2][5] = {
157  { /* for APB1 @ 36000000Hz */
158  7, /* -> 140625Hz */
159  6, /* -> 281250Hz */
160  4, /* -> 1125000Hz */
161  2, /* -> 4500000Hz */
162  1 /* -> 9000000Hz */
163  },
164  { /* for APB2 @ 72000000Hz */
165  7, /* -> 281250Hz */
166  7, /* -> 281250Hz */
167  5, /* -> 1125000Hz */
168  3, /* -> 4500000Hz */
169  2 /* -> 9000000Hz */
170  }
171 };
172 
173 static const spi_conf_t spi_config[] = {
174  {
175  .dev = SPI2,
176  .mosi_pin = GPIO_PIN(PORT_B, 15),
177  .miso_pin = GPIO_PIN(PORT_B, 14),
178  .sclk_pin = GPIO_PIN(PORT_B, 13),
179  .cs_pin = GPIO_PIN(PORT_B, 12),
180  .af = GPIO_AF5,
181  .rccmask = RCC_APB1ENR_SPI2EN,
182  .apbbus = APB1
183  }
184 };
185 
186 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
187 
193 #define I2C_NUMOF (2U)
194 #define I2C_0_EN 1
195 #define I2C_1_EN 1
196 #define I2C_IRQ_PRIO 1
197 #define I2C_APBCLK (36000000U)
198 
199 /* I2C 0 device configuration */
200 #define I2C_0_DEV I2C1
201 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
202 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
203 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
204 #define I2C_0_EVT_ISR isr_i2c1_ev
205 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
206 #define I2C_0_ERR_ISR isr_i2c1_er
207 /* I2C 0 pin configuration */
208 #define I2C_0_SCL_PORT GPIOB
209 #define I2C_0_SCL_PIN 8
210 #define I2C_0_SCL_AF 4
211 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
212 #define I2C_0_SDA_PORT GPIOB
213 #define I2C_0_SDA_PIN 9
214 #define I2C_0_SDA_AF 4
215 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
216 
217 /* I2C 1 device configuration */
218 #define I2C_1_DEV I2C3
219 #define I2C_1_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C3EN))
220 #define I2C_1_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C3EN))
221 #define I2C_1_EVT_IRQ I2C3_EV_IRQn
222 #define I2C_1_EVT_ISR isr_i2c3_ev
223 #define I2C_1_ERR_IRQ I2C3_ER_IRQn
224 #define I2C_1_ERR_ISR isr_i2c3_er
225 /* I2C 1 pin configuration */
226 #define I2C_1_SCL_PORT GPIOA
227 #define I2C_1_SCL_PIN 8
228 #define I2C_1_SCL_AF 3
229 #define I2C_1_SCL_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOAEN))
230 #define I2C_1_SDA_PORT GPIOB
231 #define I2C_1_SDA_PIN 5
232 #define I2C_1_SDA_AF 8
233 #define I2C_1_SDA_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
234 
236 #ifdef __cplusplus
237 }
238 #endif
239 
240 #endif /* PERIPH_CONF_H */
use alternate function 7
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1
PWM configuration structure.
LPC_CTxxBx_Type * dev
PWM device.
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
cc2538_ssi_t * dev
SSI device.