boards/nucleo-f302/include/periph_conf.h
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1 /*
2  * Copyright (C) 2017 Inria
3  * Copyright (C) 2015 Freie Universit├Ąt Berlin
4  * Copyright (C) 2015 Hamburg University of Applied Sciences
5  *
6  * This file is subject to the terms and conditions of the GNU Lesser
7  * General Public License v2.1. See the file LICENSE in the top level
8  * directory for more details.
9  */
10 
23 #ifndef PERIPH_CONF_H
24 #define PERIPH_CONF_H
25 
26 #include "periph_cpu.h"
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
39 /* give the target core clock (HCLK) frequency [in Hz],
40  * maximum: 72MHz */
41 #define CLOCK_CORECLOCK (72000000U)
42 /* 0: no external high speed crystal available
43  * else: actual crystal frequency [in Hz] */
44 #define CLOCK_HSE (8000000U)
45 /* 0: no external low speed crystal available,
46  * 1: external crystal available (always 32.768kHz) */
47 #define CLOCK_LSE (1)
48 /* peripheral clock setup */
49 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
50 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
51 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
52 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
53 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
54 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
55 
56 /* PLL factors */
57 #define CLOCK_PLL_PREDIV (1)
58 #define CLOCK_PLL_MUL (9)
59 
65 #define ADC_NUMOF (0)
66 
72 static const timer_conf_t timer_config[] = {
73  {
74  .dev = TIM2,
75  .max = 0xffffffff,
76  .rcc_mask = RCC_APB1ENR_TIM2EN,
77  .bus = APB1,
78  .irqn = TIM2_IRQn
79  }
80 };
81 
82 #define TIMER_0_ISR isr_tim2
83 
84 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
85 
91 static const uart_conf_t uart_config[] = {
92  {
93  .dev = USART2,
94  .rcc_mask = RCC_APB1ENR_USART2EN,
95  .rx_pin = GPIO_PIN(PORT_A, 3),
96  .tx_pin = GPIO_PIN(PORT_A, 2),
97  .rx_af = GPIO_AF7,
98  .tx_af = GPIO_AF7,
99  .bus = APB1,
100  .irqn = USART2_IRQn
101  },
102  {
103  .dev = USART1,
104  .rcc_mask = RCC_APB2ENR_USART1EN,
105  .rx_pin = GPIO_PIN(PORT_A, 10),
106  .tx_pin = GPIO_PIN(PORT_A, 9),
107  .rx_af = GPIO_AF7,
108  .tx_af = GPIO_AF7,
109  .bus = APB2,
110  .irqn = USART1_IRQn
111  },
112  {
113  .dev = USART3,
114  .rcc_mask = RCC_APB1ENR_USART3EN,
115  .rx_pin = GPIO_PIN(PORT_C, 11),
116  .tx_pin = GPIO_PIN(PORT_C, 10),
117  .rx_af = GPIO_AF7,
118  .tx_af = GPIO_AF7,
119  .bus = APB1,
120  .irqn = USART3_IRQn
121  }
122 };
123 
124 #define UART_0_ISR (isr_usart2)
125 #define UART_1_ISR (isr_usart1)
126 #define UART_2_ISR (isr_usart3)
127 
128 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
129 
135 static const pwm_conf_t pwm_config[] = {
136  {
137  .dev = TIM16,
138  .rcc_mask = RCC_APB2ENR_TIM16EN,
139  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
140  { .pin = GPIO_UNDEF, .cc_chan = 0 },
141  { .pin = GPIO_UNDEF, .cc_chan = 0 },
142  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
143  .af = GPIO_AF1,
144  .bus = APB2
145  }
146 };
147 
148 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
149 
158 static const uint8_t spi_divtable[2][5] = {
159  { /* for APB1 @ 36000000Hz */
160  7, /* -> 140625Hz */
161  6, /* -> 281250Hz */
162  4, /* -> 1125000Hz */
163  2, /* -> 4500000Hz */
164  1 /* -> 9000000Hz */
165  },
166  { /* for APB2 @ 72000000Hz */
167  7, /* -> 281250Hz */
168  7, /* -> 281250Hz */
169  5, /* -> 1125000Hz */
170  3, /* -> 4500000Hz */
171  2 /* -> 9000000Hz */
172  }
173 };
174 
175 static const spi_conf_t spi_config[] = {
176  {
177  .dev = SPI2,
178  .mosi_pin = GPIO_PIN(PORT_B, 15),
179  .miso_pin = GPIO_PIN(PORT_B, 14),
180  .sclk_pin = GPIO_PIN(PORT_B, 13),
181  .cs_pin = GPIO_PIN(PORT_B, 12),
182  .af = GPIO_AF5,
183  .rccmask = RCC_APB1ENR_SPI2EN,
184  .apbbus = APB1
185  }
186 };
187 
188 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
189 
195 #define I2C_NUMOF (2U)
196 #define I2C_0_EN 1
197 #define I2C_1_EN 1
198 #define I2C_IRQ_PRIO 1
199 #define I2C_APBCLK (36000000U)
200 
201 /* I2C 0 device configuration */
202 #define I2C_0_DEV I2C1
203 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
204 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
205 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
206 #define I2C_0_EVT_ISR isr_i2c1_ev
207 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
208 #define I2C_0_ERR_ISR isr_i2c1_er
209 /* I2C 0 pin configuration */
210 #define I2C_0_SCL_PORT GPIOB
211 #define I2C_0_SCL_PIN 8
212 #define I2C_0_SCL_AF 4
213 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
214 #define I2C_0_SDA_PORT GPIOB
215 #define I2C_0_SDA_PIN 9
216 #define I2C_0_SDA_AF 4
217 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
218 
219 /* I2C 1 device configuration */
220 #define I2C_1_DEV I2C3
221 #define I2C_1_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C3EN))
222 #define I2C_1_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C3EN))
223 #define I2C_1_EVT_IRQ I2C3_EV_IRQn
224 #define I2C_1_EVT_ISR isr_i2c3_ev
225 #define I2C_1_ERR_IRQ I2C3_ER_IRQn
226 #define I2C_1_ERR_ISR isr_i2c3_er
227 /* I2C 1 pin configuration */
228 #define I2C_1_SCL_PORT GPIOA
229 #define I2C_1_SCL_PIN 8
230 #define I2C_1_SCL_AF 3
231 #define I2C_1_SCL_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOAEN))
232 #define I2C_1_SDA_PORT GPIOB
233 #define I2C_1_SDA_PIN 5
234 #define I2C_1_SDA_AF 8
235 #define I2C_1_SDA_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
236 
238 #ifdef __cplusplus
239 }
240 #endif
241 
242 #endif /* PERIPH_CONF_H */
use alternate function 7
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1
PWM configuration structure.
NRF_TIMER_Type * dev
timer device
use alternate function 5
Tcc * dev
TCC device to use.
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI module configuration options.
Timer configuration.
cc2538_ssi_t * dev
SSI device.