boards/nucleo-f302/include/periph_conf.h
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1 /*
2  * Copyright (C) 2017 Inria
3  * Copyright (C) 2015 Freie Universit├Ąt Berlin
4  * Copyright (C) 2015 Hamburg University of Applied Sciences
5  *
6  * This file is subject to the terms and conditions of the GNU Lesser
7  * General Public License v2.1. See the file LICENSE in the top level
8  * directory for more details.
9  */
10 
23 #ifndef PERIPH_CONF_H
24 #define PERIPH_CONF_H
25 
26 #include "periph_cpu.h"
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
36 #define CLOCK_HSE (8000000U) /* external oscillator */
37 #define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
38 
39 /* the actual PLL values are automatically generated */
40 #define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE)
41 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
42 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
43 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
44 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
45 
46 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
47 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
48 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
49 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
50 
56 #define ADC_NUMOF (0)
57 
63 static const timer_conf_t timer_config[] = {
64  {
65  .dev = TIM2,
66  .max = 0xffffffff,
67  .rcc_mask = RCC_APB1ENR_TIM2EN,
68  .bus = APB1,
69  .irqn = TIM2_IRQn
70  }
71 };
72 
73 #define TIMER_0_ISR isr_tim2
74 
75 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
76 
82 static const uart_conf_t uart_config[] = {
83  {
84  .dev = USART2,
85  .rcc_mask = RCC_APB1ENR_USART2EN,
86  .rx_pin = GPIO_PIN(PORT_A, 3),
87  .tx_pin = GPIO_PIN(PORT_A, 2),
88  .rx_af = GPIO_AF7,
89  .tx_af = GPIO_AF7,
90  .bus = APB1,
91  .irqn = USART2_IRQn
92  },
93  {
94  .dev = USART1,
95  .rcc_mask = RCC_APB2ENR_USART1EN,
96  .rx_pin = GPIO_PIN(PORT_A, 10),
97  .tx_pin = GPIO_PIN(PORT_A, 9),
98  .rx_af = GPIO_AF7,
99  .tx_af = GPIO_AF7,
100  .bus = APB2,
101  .irqn = USART1_IRQn
102  },
103  {
104  .dev = USART3,
105  .rcc_mask = RCC_APB1ENR_USART3EN,
106  .rx_pin = GPIO_PIN(PORT_C, 11),
107  .tx_pin = GPIO_PIN(PORT_C, 10),
108  .rx_af = GPIO_AF7,
109  .tx_af = GPIO_AF7,
110  .bus = APB1,
111  .irqn = USART3_IRQn
112  }
113 };
114 
115 #define UART_0_ISR (isr_usart2)
116 #define UART_1_ISR (isr_usart1)
117 #define UART_2_ISR (isr_usart3)
118 
119 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
120 
126 static const pwm_conf_t pwm_config[] = {
127  {
128  .dev = TIM16,
129  .rcc_mask = RCC_APB2ENR_TIM16EN,
130  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
131  { .pin = GPIO_UNDEF, .cc_chan = 0 },
132  { .pin = GPIO_UNDEF, .cc_chan = 0 },
133  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
134  .af = GPIO_AF1,
135  .bus = APB2
136  }
137 };
138 
139 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
140 
149 static const uint8_t spi_divtable[2][5] = {
150  { /* for APB1 @ 36000000Hz */
151  7, /* -> 140625Hz */
152  6, /* -> 281250Hz */
153  4, /* -> 1125000Hz */
154  2, /* -> 4500000Hz */
155  1 /* -> 9000000Hz */
156  },
157  { /* for APB2 @ 72000000Hz */
158  7, /* -> 281250Hz */
159  7, /* -> 281250Hz */
160  5, /* -> 1125000Hz */
161  3, /* -> 4500000Hz */
162  2 /* -> 9000000Hz */
163  }
164 };
165 
166 static const spi_conf_t spi_config[] = {
167  {
168  .dev = SPI2,
169  .mosi_pin = GPIO_PIN(PORT_B, 15),
170  .miso_pin = GPIO_PIN(PORT_B, 14),
171  .sclk_pin = GPIO_PIN(PORT_B, 13),
172  .cs_pin = GPIO_PIN(PORT_B, 12),
173  .af = GPIO_AF5,
174  .rccmask = RCC_APB1ENR_SPI2EN,
175  .apbbus = APB1
176  }
177 };
178 
179 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
180 
186 #define I2C_NUMOF (2U)
187 #define I2C_0_EN 1
188 #define I2C_1_EN 1
189 #define I2C_IRQ_PRIO 1
190 #define I2C_APBCLK (36000000U)
191 
192 /* I2C 0 device configuration */
193 #define I2C_0_DEV I2C1
194 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
195 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
196 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
197 #define I2C_0_EVT_ISR isr_i2c1_ev
198 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
199 #define I2C_0_ERR_ISR isr_i2c1_er
200 /* I2C 0 pin configuration */
201 #define I2C_0_SCL_PORT GPIOB
202 #define I2C_0_SCL_PIN 8
203 #define I2C_0_SCL_AF 4
204 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
205 #define I2C_0_SDA_PORT GPIOB
206 #define I2C_0_SDA_PIN 9
207 #define I2C_0_SDA_AF 4
208 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
209 
210 /* I2C 1 device configuration */
211 #define I2C_1_DEV I2C3
212 #define I2C_1_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C3EN))
213 #define I2C_1_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C3EN))
214 #define I2C_1_EVT_IRQ I2C3_EV_IRQn
215 #define I2C_1_EVT_ISR isr_i2c3_ev
216 #define I2C_1_ERR_IRQ I2C3_ER_IRQn
217 #define I2C_1_ERR_ISR isr_i2c3_er
218 /* I2C 1 pin configuration */
219 #define I2C_1_SCL_PORT GPIOA
220 #define I2C_1_SCL_PIN 8
221 #define I2C_1_SCL_AF 3
222 #define I2C_1_SCL_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOAEN))
223 #define I2C_1_SDA_PORT GPIOB
224 #define I2C_1_SDA_PIN 5
225 #define I2C_1_SDA_AF 8
226 #define I2C_1_SDA_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
227 
229 #ifdef __cplusplus
230 }
231 #endif
232 
233 #endif /* PERIPH_CONF_H */
use alternate function 7
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1
PWM configuration structure.
LPC_CTxxBx_Type * dev
PWM device.
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
cc2538_ssi_t * dev
SSI device.