boards/nucleo-f302/include/periph_conf.h
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1 /*
2  * Copyright (C) 2017 Inria
3  * Copyright (C) 2015 Freie Universit├Ąt Berlin
4  * Copyright (C) 2015 Hamburg University of Applied Sciences
5  *
6  * This file is subject to the terms and conditions of the GNU Lesser
7  * General Public License v2.1. See the file LICENSE in the top level
8  * directory for more details.
9  */
10 
25 #ifndef PERIPH_CONF_H
26 #define PERIPH_CONF_H
27 
28 #include "periph_cpu.h"
29 
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33 
41 /* give the target core clock (HCLK) frequency [in Hz],
42  * maximum: 72MHz */
43 #define CLOCK_CORECLOCK (72000000U)
44 /* 0: no external high speed crystal available
45  * else: actual crystal frequency [in Hz] */
46 #define CLOCK_HSE (8000000U)
47 /* 0: no external low speed crystal available,
48  * 1: external crystal available (always 32.768kHz) */
49 #define CLOCK_LSE (1)
50 /* peripheral clock setup */
51 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
52 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
53 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
54 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
55 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
56 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
57 
58 /* PLL factors */
59 #define CLOCK_PLL_PREDIV (1)
60 #define CLOCK_PLL_MUL (9)
61 
67 #define ADC_NUMOF (0)
68 
74 static const timer_conf_t timer_config[] = {
75  {
76  .dev = TIM2,
77  .max = 0xffffffff,
78  .rcc_mask = RCC_APB1ENR_TIM2EN,
79  .bus = APB1,
80  .irqn = TIM2_IRQn
81  }
82 };
83 
84 #define TIMER_0_ISR isr_tim2
85 
86 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
87 
93 static const uart_conf_t uart_config[] = {
94  {
95  .dev = USART2,
96  .rcc_mask = RCC_APB1ENR_USART2EN,
97  .rx_pin = GPIO_PIN(PORT_A, 3),
98  .tx_pin = GPIO_PIN(PORT_A, 2),
99  .rx_af = GPIO_AF7,
100  .tx_af = GPIO_AF7,
101  .bus = APB1,
102  .irqn = USART2_IRQn
103  },
104  {
105  .dev = USART1,
106  .rcc_mask = RCC_APB2ENR_USART1EN,
107  .rx_pin = GPIO_PIN(PORT_A, 10),
108  .tx_pin = GPIO_PIN(PORT_A, 9),
109  .rx_af = GPIO_AF7,
110  .tx_af = GPIO_AF7,
111  .bus = APB2,
112  .irqn = USART1_IRQn
113  },
114  {
115  .dev = USART3,
116  .rcc_mask = RCC_APB1ENR_USART3EN,
117  .rx_pin = GPIO_PIN(PORT_C, 11),
118  .tx_pin = GPIO_PIN(PORT_C, 10),
119  .rx_af = GPIO_AF7,
120  .tx_af = GPIO_AF7,
121  .bus = APB1,
122  .irqn = USART3_IRQn
123  }
124 };
125 
126 #define UART_0_ISR (isr_usart2)
127 #define UART_1_ISR (isr_usart1)
128 #define UART_2_ISR (isr_usart3)
129 
130 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
131 
137 static const pwm_conf_t pwm_config[] = {
138  {
139  .dev = TIM16,
140  .rcc_mask = RCC_APB2ENR_TIM16EN,
141  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
142  { .pin = GPIO_UNDEF, .cc_chan = 0 },
143  { .pin = GPIO_UNDEF, .cc_chan = 0 },
144  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
145  .af = GPIO_AF1,
146  .bus = APB2
147  }
148 };
149 
150 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
151 
160 static const uint8_t spi_divtable[2][5] = {
161  { /* for APB1 @ 36000000Hz */
162  7, /* -> 140625Hz */
163  6, /* -> 281250Hz */
164  4, /* -> 1125000Hz */
165  2, /* -> 4500000Hz */
166  1 /* -> 9000000Hz */
167  },
168  { /* for APB2 @ 72000000Hz */
169  7, /* -> 281250Hz */
170  7, /* -> 281250Hz */
171  5, /* -> 1125000Hz */
172  3, /* -> 4500000Hz */
173  2 /* -> 9000000Hz */
174  }
175 };
176 
177 static const spi_conf_t spi_config[] = {
178  {
179  .dev = SPI2,
180  .mosi_pin = GPIO_PIN(PORT_B, 15),
181  .miso_pin = GPIO_PIN(PORT_B, 14),
182  .sclk_pin = GPIO_PIN(PORT_B, 13),
183  .cs_pin = GPIO_PIN(PORT_B, 12),
184  .af = GPIO_AF5,
185  .rccmask = RCC_APB1ENR_SPI2EN,
186  .apbbus = APB1
187  }
188 };
189 
190 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
191 
197 #define I2C_NUMOF (2U)
198 #define I2C_0_EN 1
199 #define I2C_1_EN 1
200 #define I2C_IRQ_PRIO 1
201 #define I2C_APBCLK (36000000U)
202 
203 /* I2C 0 device configuration */
204 #define I2C_0_DEV I2C1
205 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
206 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
207 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
208 #define I2C_0_EVT_ISR isr_i2c1_ev
209 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
210 #define I2C_0_ERR_ISR isr_i2c1_er
211 /* I2C 0 pin configuration */
212 #define I2C_0_SCL_PORT GPIOB
213 #define I2C_0_SCL_PIN 8
214 #define I2C_0_SCL_AF 4
215 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
216 #define I2C_0_SDA_PORT GPIOB
217 #define I2C_0_SDA_PIN 9
218 #define I2C_0_SDA_AF 4
219 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
220 
221 /* I2C 1 device configuration */
222 #define I2C_1_DEV I2C3
223 #define I2C_1_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C3EN))
224 #define I2C_1_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C3EN))
225 #define I2C_1_EVT_IRQ I2C3_EV_IRQn
226 #define I2C_1_EVT_ISR isr_i2c3_ev
227 #define I2C_1_ERR_IRQ I2C3_ER_IRQn
228 #define I2C_1_ERR_ISR isr_i2c3_er
229 /* I2C 1 pin configuration */
230 #define I2C_1_SCL_PORT GPIOA
231 #define I2C_1_SCL_PIN 8
232 #define I2C_1_SCL_AF 3
233 #define I2C_1_SCL_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOAEN))
234 #define I2C_1_SDA_PORT GPIOB
235 #define I2C_1_SDA_PIN 5
236 #define I2C_1_SDA_AF 8
237 #define I2C_1_SDA_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
238 
240 #ifdef __cplusplus
241 }
242 #endif
243 
244 #endif /* PERIPH_CONF_H */
245 
use alternate function 7
cc2538_uart_t * dev
pointer to the used UART device
TIMER_TypeDef * dev
TIMER device used.
use alternate function 1
PWM device configuration.
NRF_TIMER_Type * dev
timer device
use alternate function 5
UART device configuration.
SPI module configuration options.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Timer configuration.
cc2538_ssi_t * dev
SSI device.