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boards/nucleo-f103/include/periph_conf.h
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1 /*
2  * Copyright (C) 2015 TriaGnoSys GmbH
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 #define CLOCK_HSE (8000000U) /* external oscillator */
33 #define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
34 /* the actual PLL values are automatically generated */
35 #define CLOCK_PLL_DIV (1)
36 #define CLOCK_PLL_MUL (9)
37 /* AHB, APB1, APB2 dividers */
38 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
39 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
40 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36 MHz (!) */
41 
42 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
43 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
44 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
45 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
46 
52 #define ADC_NUMOF (0)
53 
59 #define DAC_NUMOF (0)
60 
66 static const timer_conf_t timer_config[] = {
67  {
68  .dev = TIM2,
69  .max = 0x0000ffff,
70  .rcc_mask = RCC_APB1ENR_TIM2EN,
71  .bus = APB1,
72  .irqn = TIM2_IRQn
73  },
74  {
75  .dev = TIM3,
76  .max = 0x0000ffff,
77  .rcc_mask = RCC_APB1ENR_TIM3EN,
78  .bus = APB1,
79  .irqn = TIM3_IRQn
80  }
81 };
82 
83 #define TIMER_0_ISR isr_tim2
84 #define TIMER_1_ISR isr_tim3
85 
86 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
87 
93 static const uart_conf_t uart_config[] = {
94  {
95  .dev = USART2,
96  .rcc_mask = RCC_APB1ENR_USART2EN,
97  .rx_pin = GPIO_PIN(PORT_A, 3),
98  .tx_pin = GPIO_PIN(PORT_A, 2),
99  .bus = APB1,
100  .irqn = USART2_IRQn
101  },
102  {
103  .dev = USART1,
104  .rcc_mask = RCC_APB2ENR_USART1EN,
105  .rx_pin = GPIO_PIN(PORT_A, 10),
106  .tx_pin = GPIO_PIN(PORT_A, 9),
107  .bus = APB2,
108  .irqn = USART1_IRQn
109  },
110  {
111  .dev = USART3,
112  .rcc_mask = RCC_APB1ENR_USART3EN,
113  .rx_pin = GPIO_PIN(PORT_B, 11),
114  .tx_pin = GPIO_PIN(PORT_B, 10),
115  .bus = APB1,
116  .irqn = USART3_IRQn
117  }
118 };
119 
120 #define UART_0_ISR (isr_usart2)
121 #define UART_1_ISR (isr_usart1)
122 #define UART_2_ISR (isr_usart3)
123 
124 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
125 
131 #define I2C_NUMOF (2U)
132 #define I2C_0_EN 1
133 #define I2C_1_EN 0
134 #define I2C_IRQ_PRIO 1
135 #define I2C_APBCLK (36000000U)
136 
137 /* I2C 0 device configuration */
138 #define I2C_0_DEV I2C1
139 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
140 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
141 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
142 #define I2C_0_EVT_ISR isr_i2c1_ev
143 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
144 #define I2C_0_ERR_ISR isr_i2c1_er
145 /* I2C 0 pin configuration */
146 #define I2C_0_SCL_PIN GPIO_PIN(PORT_B, 8) /* remapped */
147 #define I2C_0_SDA_PIN GPIO_PIN(PORT_B, 9) /* remapped */
148 
149 /* I2C 1 device configuration */
150 #define I2C_1_DEV I2C2
151 #define I2C_1_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C2EN))
152 #define I2C_1_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C2EN))
153 #define I2C_1_EVT_IRQ I2C2_EV_IRQn
154 #define I2C_1_EVT_ISR isr_i2c2_ev
155 #define I2C_1_ERR_IRQ I2C2_ER_IRQn
156 #define I2C_1_ERR_ISR isr_i2c2_er
157 /* I2C 1 pin configuration */
158 #define I2C_1_SCL_PIN GPIO_PIN(PORT_B, 10)
159 #define I2C_1_SDA_PIN GPIO_PIN(PORT_B, 11)
160 
169 static const uint8_t spi_divtable[2][5] = {
170  { /* for APB1 @ 36000000Hz */
171  7, /* -> 140625Hz */
172  6, /* -> 281250Hz */
173  4, /* -> 1125000Hz */
174  2, /* -> 4500000Hz */
175  1 /* -> 9000000Hz */
176  },
177  { /* for APB2 @ 72000000Hz */
178  7, /* -> 281250Hz */
179  7, /* -> 281250Hz */
180  5, /* -> 1125000Hz */
181  3, /* -> 4500000Hz */
182  2 /* -> 9000000Hz */
183  }
184 };
185 
186 static const spi_conf_t spi_config[] = {
187  {
188  .dev = SPI1,
189  .mosi_pin = GPIO_PIN(PORT_A, 7),
190  .miso_pin = GPIO_PIN(PORT_A, 6),
191  .sclk_pin = GPIO_PIN(PORT_A, 5),
192  .cs_pin = GPIO_UNDEF,
193  .rccmask = RCC_APB2ENR_SPI1EN,
194  .apbbus = APB2
195  },
196  {
197  .dev = SPI2,
198  .mosi_pin = GPIO_PIN(PORT_B, 15),
199  .miso_pin = GPIO_PIN(PORT_B, 14),
200  .sclk_pin = GPIO_PIN(PORT_B, 13),
201  .cs_pin = GPIO_UNDEF,
202  .rccmask = RCC_APB1ENR_SPI2EN,
203  .apbbus = APB1
204  }
205 };
206 
207 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
208 
210 #ifdef __cplusplus
211 }
212 #endif
213 
214 #endif /* PERIPH_CONF_H */
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
cc2538_ssi_t * dev
SSI device.