boards/nucleo-f103/include/periph_conf.h
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1 /*
2  * Copyright (C) 2015 TriaGnoSys GmbH
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 /* high speed clock configuration:
33  * 0 := use internal HSI oscillator (always 8MHz)
34  * HSE frequency value := use external HSE oscillator with given freq [in Hz]
35  * must be 4000000 <= value <= 16000000 */
36 #define CLOCK_HSE (8000000U)
37 /* low speed clock configuration:
38  * 0 := use internal LSI oscillator (~40kHz)
39  * 1 := use extern LSE oscillator, always 32.768kHz */
40 #define CLOCK_LSE (1)
41 /* targeted system clock speed [in Hz], must be <= 72MHz */
42 #define CLOCK_CORECLOCK (72000000U)
43 /* PLL configuration, set both values to zero to disable PLL usage. The values
44  * must be set to satisfy the following equation:
45  * CORECLOCK := CLOCK_SOURCE / PLL_DIV * PLL_MUL
46  * with
47  * 1 <= CLOCK_PLL_DIV <= 2
48  * 2 <= CLOCK_PLL_MUL <= 17 */
49 #define CLOCK_PLL_DIV (1)
50 #define CLOCK_PLL_MUL (9)
51 /* AHB and APBx bus clock configuration, keep in mind the following constraints:
52  * ABP1 <= 36MHz
53  */
54 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
55 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
56 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
57 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
58 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
59 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
60 
66 #define ADC_NUMOF (0)
67 
73 #define DAC_NUMOF (0)
74 
80 static const timer_conf_t timer_config[] = {
81  {
82  .dev = TIM2,
83  .max = 0x0000ffff,
84  .rcc_mask = RCC_APB1ENR_TIM2EN,
85  .bus = APB1,
86  .irqn = TIM2_IRQn
87  },
88  {
89  .dev = TIM3,
90  .max = 0x0000ffff,
91  .rcc_mask = RCC_APB1ENR_TIM3EN,
92  .bus = APB1,
93  .irqn = TIM3_IRQn
94  }
95 };
96 
97 #define TIMER_0_ISR isr_tim2
98 #define TIMER_1_ISR isr_tim3
99 
100 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
101 
107 static const uart_conf_t uart_config[] = {
108  {
109  .dev = USART2,
110  .rcc_mask = RCC_APB1ENR_USART2EN,
111  .rx_pin = GPIO_PIN(PORT_A, 3),
112  .tx_pin = GPIO_PIN(PORT_A, 2),
113  .bus = APB1,
114  .irqn = USART2_IRQn
115  },
116  {
117  .dev = USART1,
118  .rcc_mask = RCC_APB2ENR_USART1EN,
119  .rx_pin = GPIO_PIN(PORT_A, 10),
120  .tx_pin = GPIO_PIN(PORT_A, 9),
121  .bus = APB2,
122  .irqn = USART1_IRQn
123  },
124  {
125  .dev = USART3,
126  .rcc_mask = RCC_APB1ENR_USART3EN,
127  .rx_pin = GPIO_PIN(PORT_B, 11),
128  .tx_pin = GPIO_PIN(PORT_B, 10),
129  .bus = APB1,
130  .irqn = USART3_IRQn
131  }
132 };
133 
134 #define UART_0_ISR (isr_usart2)
135 #define UART_1_ISR (isr_usart1)
136 #define UART_2_ISR (isr_usart3)
137 
138 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
139 
145 #define I2C_NUMOF (2U)
146 #define I2C_0_EN 1
147 #define I2C_1_EN 0
148 #define I2C_IRQ_PRIO 1
149 #define I2C_APBCLK (CLOCK_APB1)
150 
151 /* I2C 0 device configuration */
152 #define I2C_0_DEV I2C1
153 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
154 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
155 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
156 #define I2C_0_EVT_ISR isr_i2c1_ev
157 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
158 #define I2C_0_ERR_ISR isr_i2c1_er
159 /* I2C 0 pin configuration */
160 #define I2C_0_SCL_PIN GPIO_PIN(PORT_B, 8) /* remapped */
161 #define I2C_0_SDA_PIN GPIO_PIN(PORT_B, 9) /* remapped */
162 
163 /* I2C 1 device configuration */
164 #define I2C_1_DEV I2C2
165 #define I2C_1_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C2EN))
166 #define I2C_1_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C2EN))
167 #define I2C_1_EVT_IRQ I2C2_EV_IRQn
168 #define I2C_1_EVT_ISR isr_i2c2_ev
169 #define I2C_1_ERR_IRQ I2C2_ER_IRQn
170 #define I2C_1_ERR_ISR isr_i2c2_er
171 /* I2C 1 pin configuration */
172 #define I2C_1_SCL_PIN GPIO_PIN(PORT_B, 10)
173 #define I2C_1_SDA_PIN GPIO_PIN(PORT_B, 11)
174 
183 static const uint8_t spi_divtable[2][5] = {
184  { /* for APB1 @ 36000000Hz */
185  7, /* -> 140625Hz */
186  6, /* -> 281250Hz */
187  4, /* -> 1125000Hz */
188  2, /* -> 4500000Hz */
189  1 /* -> 9000000Hz */
190  },
191  { /* for APB2 @ 72000000Hz */
192  7, /* -> 281250Hz */
193  7, /* -> 281250Hz */
194  5, /* -> 1125000Hz */
195  3, /* -> 4500000Hz */
196  2 /* -> 9000000Hz */
197  }
198 };
199 
200 static const spi_conf_t spi_config[] = {
201  {
202  .dev = SPI1,
203  .mosi_pin = GPIO_PIN(PORT_A, 7),
204  .miso_pin = GPIO_PIN(PORT_A, 6),
205  .sclk_pin = GPIO_PIN(PORT_A, 5),
206  .cs_pin = GPIO_UNDEF,
207  .rccmask = RCC_APB2ENR_SPI1EN,
208  .apbbus = APB2
209  },
210  {
211  .dev = SPI2,
212  .mosi_pin = GPIO_PIN(PORT_B, 15),
213  .miso_pin = GPIO_PIN(PORT_B, 14),
214  .sclk_pin = GPIO_PIN(PORT_B, 13),
215  .cs_pin = GPIO_UNDEF,
216  .rccmask = RCC_APB1ENR_SPI2EN,
217  .apbbus = APB1
218  }
219 };
220 
221 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
222 
224 #ifdef __cplusplus
225 }
226 #endif
227 
228 #endif /* PERIPH_CONF_H */
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
cc2538_ssi_t * dev
SSI device.