boards/nucleo-f103/include/periph_conf.h
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1 /*
2  * Copyright (C) 2015 TriaGnoSys GmbH
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
35 /* give the target core clock (HCLK) frequency [in Hz],
36  * maximum: 72MHz */
37 #define CLOCK_CORECLOCK (72000000U)
38 /* 0: no external high speed crystal available
39  * else: actual crystal frequency [in Hz] */
40 #define CLOCK_HSE (8000000U)
41 /* 0: no external low speed crystal available,
42  * 1: external crystal available (always 32.768kHz) */
43 #define CLOCK_LSE (1)
44 /* peripheral clock setup */
45 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
46 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
47 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
48 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
49 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
50 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
51 
52 /* PLL factors */
53 #define CLOCK_PLL_PREDIV (1)
54 #define CLOCK_PLL_MUL (9)
55 
61 #define ADC_NUMOF (0)
62 
68 static const timer_conf_t timer_config[] = {
69  {
70  .dev = TIM2,
71  .max = 0x0000ffff,
72  .rcc_mask = RCC_APB1ENR_TIM2EN,
73  .bus = APB1,
74  .irqn = TIM2_IRQn
75  },
76  {
77  .dev = TIM3,
78  .max = 0x0000ffff,
79  .rcc_mask = RCC_APB1ENR_TIM3EN,
80  .bus = APB1,
81  .irqn = TIM3_IRQn
82  }
83 };
84 
85 #define TIMER_0_ISR isr_tim2
86 #define TIMER_1_ISR isr_tim3
87 
88 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
89 
95 static const uart_conf_t uart_config[] = {
96  {
97  .dev = USART2,
98  .rcc_mask = RCC_APB1ENR_USART2EN,
99  .rx_pin = GPIO_PIN(PORT_A, 3),
100  .tx_pin = GPIO_PIN(PORT_A, 2),
101  .bus = APB1,
102  .irqn = USART2_IRQn
103  },
104  {
105  .dev = USART1,
106  .rcc_mask = RCC_APB2ENR_USART1EN,
107  .rx_pin = GPIO_PIN(PORT_A, 10),
108  .tx_pin = GPIO_PIN(PORT_A, 9),
109  .bus = APB2,
110  .irqn = USART1_IRQn
111  },
112  {
113  .dev = USART3,
114  .rcc_mask = RCC_APB1ENR_USART3EN,
115  .rx_pin = GPIO_PIN(PORT_B, 11),
116  .tx_pin = GPIO_PIN(PORT_B, 10),
117  .bus = APB1,
118  .irqn = USART3_IRQn
119  }
120 };
121 
122 #define UART_0_ISR (isr_usart2)
123 #define UART_1_ISR (isr_usart1)
124 #define UART_2_ISR (isr_usart3)
125 
126 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
127 
133 #define I2C_NUMOF (2U)
134 #define I2C_0_EN 1
135 #define I2C_1_EN 0
136 #define I2C_IRQ_PRIO 1
137 #define I2C_APBCLK (CLOCK_APB1)
138 
139 /* I2C 0 device configuration */
140 #define I2C_0_DEV I2C1
141 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
142 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
143 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
144 #define I2C_0_EVT_ISR isr_i2c1_ev
145 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
146 #define I2C_0_ERR_ISR isr_i2c1_er
147 /* I2C 0 pin configuration */
148 #define I2C_0_SCL_PIN GPIO_PIN(PORT_B, 8) /* remapped */
149 #define I2C_0_SDA_PIN GPIO_PIN(PORT_B, 9) /* remapped */
150 
151 /* I2C 1 device configuration */
152 #define I2C_1_DEV I2C2
153 #define I2C_1_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C2EN))
154 #define I2C_1_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C2EN))
155 #define I2C_1_EVT_IRQ I2C2_EV_IRQn
156 #define I2C_1_EVT_ISR isr_i2c2_ev
157 #define I2C_1_ERR_IRQ I2C2_ER_IRQn
158 #define I2C_1_ERR_ISR isr_i2c2_er
159 /* I2C 1 pin configuration */
160 #define I2C_1_SCL_PIN GPIO_PIN(PORT_B, 10)
161 #define I2C_1_SDA_PIN GPIO_PIN(PORT_B, 11)
162 
171 static const uint8_t spi_divtable[2][5] = {
172  { /* for APB1 @ 36000000Hz */
173  7, /* -> 140625Hz */
174  6, /* -> 281250Hz */
175  4, /* -> 1125000Hz */
176  2, /* -> 4500000Hz */
177  1 /* -> 9000000Hz */
178  },
179  { /* for APB2 @ 72000000Hz */
180  7, /* -> 281250Hz */
181  7, /* -> 281250Hz */
182  5, /* -> 1125000Hz */
183  3, /* -> 4500000Hz */
184  2 /* -> 9000000Hz */
185  }
186 };
187 
188 static const spi_conf_t spi_config[] = {
189  {
190  .dev = SPI1,
191  .mosi_pin = GPIO_PIN(PORT_A, 7),
192  .miso_pin = GPIO_PIN(PORT_A, 6),
193  .sclk_pin = GPIO_PIN(PORT_A, 5),
194  .cs_pin = GPIO_UNDEF,
195  .rccmask = RCC_APB2ENR_SPI1EN,
196  .apbbus = APB2
197  },
198  {
199  .dev = SPI2,
200  .mosi_pin = GPIO_PIN(PORT_B, 15),
201  .miso_pin = GPIO_PIN(PORT_B, 14),
202  .sclk_pin = GPIO_PIN(PORT_B, 13),
203  .cs_pin = GPIO_UNDEF,
204  .rccmask = RCC_APB1ENR_SPI2EN,
205  .apbbus = APB1
206  }
207 };
208 
209 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
210 
212 #ifdef __cplusplus
213 }
214 #endif
215 
216 #endif /* PERIPH_CONF_H */
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
NRF_TIMER_Type * dev
timer device
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI module configuration options.
Timer configuration.
cc2538_ssi_t * dev
SSI device.