boards/nucleo-f103/include/periph_conf.h
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1 /*
2  * Copyright (C) 2015 TriaGnoSys GmbH
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 #include "periph_cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
37 /* give the target core clock (HCLK) frequency [in Hz],
38  * maximum: 72MHz */
39 #define CLOCK_CORECLOCK (72000000U)
40 /* 0: no external high speed crystal available
41  * else: actual crystal frequency [in Hz] */
42 #define CLOCK_HSE (8000000U)
43 /* 0: no external low speed crystal available,
44  * 1: external crystal available (always 32.768kHz) */
45 #define CLOCK_LSE (1)
46 /* peripheral clock setup */
47 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
48 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
49 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
50 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
51 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
52 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
53 
54 /* PLL factors */
55 #define CLOCK_PLL_PREDIV (1)
56 #define CLOCK_PLL_MUL (9)
57 
63 #define ADC_NUMOF (0)
64 
70 static const timer_conf_t timer_config[] = {
71  {
72  .dev = TIM2,
73  .max = 0x0000ffff,
74  .rcc_mask = RCC_APB1ENR_TIM2EN,
75  .bus = APB1,
76  .irqn = TIM2_IRQn
77  },
78  {
79  .dev = TIM3,
80  .max = 0x0000ffff,
81  .rcc_mask = RCC_APB1ENR_TIM3EN,
82  .bus = APB1,
83  .irqn = TIM3_IRQn
84  }
85 };
86 
87 #define TIMER_0_ISR isr_tim2
88 #define TIMER_1_ISR isr_tim3
89 
90 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
91 
97 static const uart_conf_t uart_config[] = {
98  {
99  .dev = USART2,
100  .rcc_mask = RCC_APB1ENR_USART2EN,
101  .rx_pin = GPIO_PIN(PORT_A, 3),
102  .tx_pin = GPIO_PIN(PORT_A, 2),
103  .bus = APB1,
104  .irqn = USART2_IRQn
105  },
106  {
107  .dev = USART1,
108  .rcc_mask = RCC_APB2ENR_USART1EN,
109  .rx_pin = GPIO_PIN(PORT_A, 10),
110  .tx_pin = GPIO_PIN(PORT_A, 9),
111  .bus = APB2,
112  .irqn = USART1_IRQn
113  },
114  {
115  .dev = USART3,
116  .rcc_mask = RCC_APB1ENR_USART3EN,
117  .rx_pin = GPIO_PIN(PORT_B, 11),
118  .tx_pin = GPIO_PIN(PORT_B, 10),
119  .bus = APB1,
120  .irqn = USART3_IRQn
121  }
122 };
123 
124 #define UART_0_ISR (isr_usart2)
125 #define UART_1_ISR (isr_usart1)
126 #define UART_2_ISR (isr_usart3)
127 
128 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
129 
135 #define RTT_NUMOF (1U)
136 #define RTT_IRQ_PRIO 1
137 
138 #define RTT_DEV RTC
139 #define RTT_IRQ RTC_IRQn
140 #define RTT_ISR isr_rtc
141 #define RTT_MAX_VALUE (0xffffffff)
142 #define RTT_FREQUENCY (16384) /* in Hz */
143 #define RTT_PRESCALER (0x1) /* run with ~16 kHz Hz */
144 
150 #define I2C_NUMOF (2U)
151 #define I2C_0_EN 1
152 #define I2C_1_EN 0
153 #define I2C_IRQ_PRIO 1
154 #define I2C_APBCLK (CLOCK_APB1)
155 
156 /* I2C 0 device configuration */
157 #define I2C_0_DEV I2C1
158 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
159 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
160 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
161 #define I2C_0_EVT_ISR isr_i2c1_ev
162 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
163 #define I2C_0_ERR_ISR isr_i2c1_er
164 /* I2C 0 pin configuration */
165 #define I2C_0_SCL_PIN GPIO_PIN(PORT_B, 8) /* remapped */
166 #define I2C_0_SDA_PIN GPIO_PIN(PORT_B, 9) /* remapped */
167 
168 /* I2C 1 device configuration */
169 #define I2C_1_DEV I2C2
170 #define I2C_1_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C2EN))
171 #define I2C_1_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C2EN))
172 #define I2C_1_EVT_IRQ I2C2_EV_IRQn
173 #define I2C_1_EVT_ISR isr_i2c2_ev
174 #define I2C_1_ERR_IRQ I2C2_ER_IRQn
175 #define I2C_1_ERR_ISR isr_i2c2_er
176 /* I2C 1 pin configuration */
177 #define I2C_1_SCL_PIN GPIO_PIN(PORT_B, 10)
178 #define I2C_1_SDA_PIN GPIO_PIN(PORT_B, 11)
179 
188 static const uint8_t spi_divtable[2][5] = {
189  { /* for APB1 @ 36000000Hz */
190  7, /* -> 140625Hz */
191  6, /* -> 281250Hz */
192  4, /* -> 1125000Hz */
193  2, /* -> 4500000Hz */
194  1 /* -> 9000000Hz */
195  },
196  { /* for APB2 @ 72000000Hz */
197  7, /* -> 281250Hz */
198  7, /* -> 281250Hz */
199  5, /* -> 1125000Hz */
200  3, /* -> 4500000Hz */
201  2 /* -> 9000000Hz */
202  }
203 };
204 
205 static const spi_conf_t spi_config[] = {
206  {
207  .dev = SPI1,
208  .mosi_pin = GPIO_PIN(PORT_A, 7),
209  .miso_pin = GPIO_PIN(PORT_A, 6),
210  .sclk_pin = GPIO_PIN(PORT_A, 5),
211  .cs_pin = GPIO_UNDEF,
212  .rccmask = RCC_APB2ENR_SPI1EN,
213  .apbbus = APB2
214  },
215  {
216  .dev = SPI2,
217  .mosi_pin = GPIO_PIN(PORT_B, 15),
218  .miso_pin = GPIO_PIN(PORT_B, 14),
219  .sclk_pin = GPIO_PIN(PORT_B, 13),
220  .cs_pin = GPIO_UNDEF,
221  .rccmask = RCC_APB1ENR_SPI2EN,
222  .apbbus = APB1
223  }
224 };
225 
226 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
227 
229 #ifdef __cplusplus
230 }
231 #endif
232 
233 #endif /* PERIPH_CONF_H */
234 
cc2538_uart_t * dev
pointer to the used UART device
NRF_TIMER_Type * dev
timer device
UART device configuration.
SPI module configuration options.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Timer configuration.
cc2538_ssi_t * dev
SSI device.