boards/nucleo-f091/include/periph_conf.h
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1 /*
2  * Copyright (C) 2015 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
35 /* give the target core clock (HCLK) frequency [in Hz],
36  * maximum: 48MHz */
37 #define CLOCK_CORECLOCK (48000000U)
38 /* 0: no external high speed crystal available
39  * else: actual crystal frequency [in Hz] */
40 #define CLOCK_HSE (8000000U)
41 /* 0: no external low speed crystal available,
42  * 1: external crystal available (always 32.768kHz) */
43 #define CLOCK_LSE (1)
44 /* peripheral clock setup */
45 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
46 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
47 #define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
48 #define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
49 #define CLOCK_APB2 (CLOCK_APB1)
50 
51 /* PLL factors */
52 #define CLOCK_PLL_PREDIV (1)
53 #define CLOCK_PLL_MUL (6)
54 
60 static const timer_conf_t timer_config[] = {
61  {
62  .dev = TIM1,
63  .max = 0x0000ffff,
64  .rcc_mask = RCC_APB2ENR_TIM1EN,
65  .bus = APB2,
66  .irqn = TIM1_CC_IRQn
67  }
68 };
69 
70 #define TIMER_0_ISR isr_tim1_cc
71 
72 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
73 
79 static const uart_conf_t uart_config[] = {
80  {
81  .dev = USART2,
82  .rcc_mask = RCC_APB1ENR_USART2EN,
83  .rx_pin = GPIO_PIN(PORT_A, 3),
84  .tx_pin = GPIO_PIN(PORT_A, 2),
85  .rx_af = GPIO_AF1,
86  .tx_af = GPIO_AF1,
87  .bus = APB1,
88  .irqn = USART2_IRQn
89  },
90  {
91  .dev = USART1,
92  .rcc_mask = RCC_APB2ENR_USART1EN,
93  .rx_pin = GPIO_PIN(PORT_A, 10),
94  .tx_pin = GPIO_PIN(PORT_A, 9),
95  .rx_af = GPIO_AF1,
96  .tx_af = GPIO_AF1,
97  .bus = APB2,
98  .irqn = USART1_IRQn
99  },
100  {
101  .dev = USART3,
102  .rcc_mask = RCC_APB1ENR_USART3EN,
103  .rx_pin = GPIO_PIN(PORT_C, 11),
104  .tx_pin = GPIO_PIN(PORT_C, 10),
105  .rx_af = GPIO_AF1,
106  .tx_af = GPIO_AF1,
107  .bus = APB1,
108  .irqn = USART3_8_IRQn
109  },
110 };
111 
112 #define UART_0_ISR (isr_usart2)
113 #define UART_1_ISR (isr_usart1)
114 #define UART_2_ISR (isr_usart3_8)
115 
116 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
117 
127 static const uint8_t spi_divtable[2][5] = {
128  { /* for APB1 @ 48000000Hz */
129  7, /* -> 187500Hz */
130  6, /* -> 375000Hz */
131  5, /* -> 750000Hz */
132  2, /* -> 6000000Hz */
133  1 /* -> 12000000Hz */
134  },
135  { /* for APB2 @ 48000000Hz */
136  7, /* -> 187500Hz */
137  6, /* -> 375000Hz */
138  5, /* -> 750000Hz */
139  2, /* -> 6000000Hz */
140  1 /* -> 12000000Hz */
141  }
142 };
143 
144 static const spi_conf_t spi_config[] = {
145  {
146  .dev = SPI1,
147  .mosi_pin = GPIO_PIN(PORT_A, 7),
148  .miso_pin = GPIO_PIN(PORT_A, 6),
149  .sclk_pin = GPIO_PIN(PORT_A, 5),
150  .cs_pin = GPIO_PIN(PORT_B, 6),
151  .af = GPIO_AF0,
152  .rccmask = RCC_APB2ENR_SPI1EN,
153  .apbbus = APB2
154  }
155 };
156 
157 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
158 
165 static const pwm_conf_t pwm_config[] = {
166  {
167  .dev = TIM2,
168  .rcc_mask = RCC_APB1ENR_TIM2EN,
169  .chan = { { .pin = GPIO_PIN(PORT_B, 3) /* D3 */, .cc_chan = 1 },
170  { .pin = GPIO_PIN(PORT_B, 10) /* D6 */, .cc_chan = 2 },
171  { .pin = GPIO_PIN(PORT_B, 11) , .cc_chan = 3 },
172  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
173  .af = GPIO_AF2,
174  .bus = APB1
175  },
176  {
177  .dev = TIM3,
178  .rcc_mask = RCC_APB1ENR_TIM3EN,
179  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
180  { .pin = GPIO_PIN(PORT_C, 7) /* D9 */, .cc_chan = 1 },
181  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
182  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
183  .af = GPIO_AF0,
184  .bus = APB1
185  }
186 };
187 
188 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
189 
200 #define RTC_NUMOF (1U)
201 
207 #define ADC_CONFIG { \
208  { GPIO_PIN(PORT_A, 0), 0 },\
209  { GPIO_PIN(PORT_A, 1), 1 },\
210  { GPIO_PIN(PORT_A, 4), 4 },\
211  { GPIO_PIN(PORT_B, 0), 8 },\
212  { GPIO_PIN(PORT_C, 1), 11 },\
213  { GPIO_PIN(PORT_C, 0), 10 } \
214 }
215 
216 #define ADC_NUMOF (6)
217 
219 #ifdef __cplusplus
220 }
221 #endif
222 
223 #endif /* PERIPH_CONF_H */
224 
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1
PWM configuration structure.
NRF_TIMER_Type * dev
timer device
use alternate function 0
Tcc * dev
TCC device to use.
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI module configuration options.
Timer configuration.
use alternate function 2
cc2538_ssi_t * dev
SSI device.