boards/nucleo-f091/include/periph_conf.h
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1 /*
2  * Copyright (C) 2015 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 #include "periph_cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
37 /* give the target core clock (HCLK) frequency [in Hz],
38  * maximum: 48MHz */
39 #define CLOCK_CORECLOCK (48000000U)
40 /* 0: no external high speed crystal available
41  * else: actual crystal frequency [in Hz] */
42 #define CLOCK_HSE (8000000U)
43 /* 0: no external low speed crystal available,
44  * 1: external crystal available (always 32.768kHz) */
45 #define CLOCK_LSE (1)
46 /* peripheral clock setup */
47 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
48 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
49 #define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
50 #define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
51 #define CLOCK_APB2 (CLOCK_APB1)
52 
53 /* PLL factors */
54 #define CLOCK_PLL_PREDIV (1)
55 #define CLOCK_PLL_MUL (6)
56 
62 static const timer_conf_t timer_config[] = {
63  {
64  .dev = TIM1,
65  .max = 0x0000ffff,
66  .rcc_mask = RCC_APB2ENR_TIM1EN,
67  .bus = APB2,
68  .irqn = TIM1_CC_IRQn
69  }
70 };
71 
72 #define TIMER_0_ISR isr_tim1_cc
73 
74 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
75 
81 static const uart_conf_t uart_config[] = {
82  {
83  .dev = USART2,
84  .rcc_mask = RCC_APB1ENR_USART2EN,
85  .rx_pin = GPIO_PIN(PORT_A, 3),
86  .tx_pin = GPIO_PIN(PORT_A, 2),
87  .rx_af = GPIO_AF1,
88  .tx_af = GPIO_AF1,
89  .bus = APB1,
90  .irqn = USART2_IRQn
91  },
92  {
93  .dev = USART1,
94  .rcc_mask = RCC_APB2ENR_USART1EN,
95  .rx_pin = GPIO_PIN(PORT_A, 10),
96  .tx_pin = GPIO_PIN(PORT_A, 9),
97  .rx_af = GPIO_AF1,
98  .tx_af = GPIO_AF1,
99  .bus = APB2,
100  .irqn = USART1_IRQn
101  },
102  {
103  .dev = USART3,
104  .rcc_mask = RCC_APB1ENR_USART3EN,
105  .rx_pin = GPIO_PIN(PORT_C, 11),
106  .tx_pin = GPIO_PIN(PORT_C, 10),
107  .rx_af = GPIO_AF1,
108  .tx_af = GPIO_AF1,
109  .bus = APB1,
110  .irqn = USART3_8_IRQn
111  },
112 };
113 
114 #define UART_0_ISR (isr_usart2)
115 #define UART_1_ISR (isr_usart1)
116 #define UART_2_ISR (isr_usart3_8)
117 
118 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
119 
129 static const uint8_t spi_divtable[2][5] = {
130  { /* for APB1 @ 48000000Hz */
131  7, /* -> 187500Hz */
132  6, /* -> 375000Hz */
133  5, /* -> 750000Hz */
134  2, /* -> 6000000Hz */
135  1 /* -> 12000000Hz */
136  },
137  { /* for APB2 @ 48000000Hz */
138  7, /* -> 187500Hz */
139  6, /* -> 375000Hz */
140  5, /* -> 750000Hz */
141  2, /* -> 6000000Hz */
142  1 /* -> 12000000Hz */
143  }
144 };
145 
146 static const spi_conf_t spi_config[] = {
147  {
148  .dev = SPI1,
149  .mosi_pin = GPIO_PIN(PORT_A, 7),
150  .miso_pin = GPIO_PIN(PORT_A, 6),
151  .sclk_pin = GPIO_PIN(PORT_A, 5),
152  .cs_pin = GPIO_PIN(PORT_B, 6),
153  .af = GPIO_AF0,
154  .rccmask = RCC_APB2ENR_SPI1EN,
155  .apbbus = APB2
156  }
157 };
158 
159 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
160 
167 static const pwm_conf_t pwm_config[] = {
168  {
169  .dev = TIM2,
170  .rcc_mask = RCC_APB1ENR_TIM2EN,
171  .chan = { { .pin = GPIO_PIN(PORT_B, 3) /* D3 */, .cc_chan = 1 },
172  { .pin = GPIO_PIN(PORT_B, 10) /* D6 */, .cc_chan = 2 },
173  { .pin = GPIO_PIN(PORT_B, 11) , .cc_chan = 3 },
174  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
175  .af = GPIO_AF2,
176  .bus = APB1
177  },
178  {
179  .dev = TIM3,
180  .rcc_mask = RCC_APB1ENR_TIM3EN,
181  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
182  { .pin = GPIO_PIN(PORT_C, 7) /* D9 */, .cc_chan = 1 },
183  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
184  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
185  .af = GPIO_AF0,
186  .bus = APB1
187  }
188 };
189 
190 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
191 
202 #define RTC_NUMOF (1U)
203 
209 #define ADC_CONFIG { \
210  { GPIO_PIN(PORT_A, 0), 0 },\
211  { GPIO_PIN(PORT_A, 1), 1 },\
212  { GPIO_PIN(PORT_A, 4), 4 },\
213  { GPIO_PIN(PORT_B, 0), 8 },\
214  { GPIO_PIN(PORT_C, 1), 11 },\
215  { GPIO_PIN(PORT_C, 0), 10 } \
216 }
217 
218 #define ADC_NUMOF (6)
219 
221 #ifdef __cplusplus
222 }
223 #endif
224 
225 #endif /* PERIPH_CONF_H */
226 
cc2538_uart_t * dev
pointer to the used UART device
TIMER_TypeDef * dev
TIMER device used.
use alternate function 1
PWM device configuration.
NRF_TIMER_Type * dev
timer device
use alternate function 0
UART device configuration.
SPI module configuration options.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Timer configuration.
use alternate function 2
cc2538_ssi_t * dev
SSI device.