boards/nucleo-f072/include/periph_conf.h
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1 /*
2  * Copyright (C) 2015 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
22 #ifndef PERIPH_CONF_H
23 #define PERIPH_CONF_H
24 
25 #include "periph_cpu.h"
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30 
38 /* give the target core clock (HCLK) frequency [in Hz],
39  * maximum: 48MHz */
40  #define CLOCK_CORECLOCK (48000000U)
41  /* 0: no external high speed crystal available
42  * else: actual crystal frequency [in Hz] */
43  #define CLOCK_HSE (8000000U)
44  /* 0: no external low speed crystal available,
45  * 1: external crystal available (always 32.768kHz) */
46  #define CLOCK_LSE (1)
47  /* peripheral clock setup */
48  #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
49  #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
50  #define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
51  #define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
52  #define CLOCK_APB2 (CLOCK_APB1)
53 
54  /* PLL factors */
55  #define CLOCK_PLL_PREDIV (1)
56  #define CLOCK_PLL_MUL (6)
57 
63 static const timer_conf_t timer_config[] = {
64  {
65  .dev = TIM1,
66  .max = 0x0000ffff,
67  .rcc_mask = RCC_APB2ENR_TIM1EN,
68  .bus = APB2,
69  .irqn = TIM1_CC_IRQn
70  }
71 };
72 
73 #define TIMER_0_ISR isr_tim1_cc
74 
75 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
76 
82 static const uart_conf_t uart_config[] = {
83  {
84  .dev = USART2,
85  .rcc_mask = RCC_APB1ENR_USART2EN,
86  .rx_pin = GPIO_PIN(PORT_A, 3),
87  .tx_pin = GPIO_PIN(PORT_A, 2),
88  .rx_af = GPIO_AF1,
89  .tx_af = GPIO_AF1,
90  .bus = APB1,
91  .irqn = USART2_IRQn
92  },
93  {
94  .dev = USART1,
95  .rcc_mask = RCC_APB2ENR_USART1EN,
96  .rx_pin = GPIO_PIN(PORT_A, 10),
97  .tx_pin = GPIO_PIN(PORT_A, 9),
98  .rx_af = GPIO_AF1,
99  .tx_af = GPIO_AF1,
100  .bus = APB2,
101  .irqn = USART1_IRQn
102  },
103  {
104  .dev = USART3,
105  .rcc_mask = RCC_APB1ENR_USART3EN,
106  .rx_pin = GPIO_PIN(PORT_C, 11),
107  .tx_pin = GPIO_PIN(PORT_C, 10),
108  .rx_af = GPIO_AF1,
109  .tx_af = GPIO_AF1,
110  .bus = APB1,
111  .irqn = USART3_8_IRQn
112  }
113 };
114 
115 #define UART_0_ISR (isr_usart2)
116 #define UART_1_ISR (isr_usart1)
117 #define UART_2_ISR (isr_usart3_8)
118 
119 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
120 
126 static const pwm_conf_t pwm_config[] = {
127  {
128  .dev = TIM2,
129  .rcc_mask = RCC_APB1ENR_TIM2EN,
130  .chan = { { .pin = GPIO_PIN(PORT_B, 3) /* D3 */, .cc_chan = 1 },
131  { .pin = GPIO_PIN(PORT_B, 10) /* D6 */, .cc_chan = 2 },
132  { .pin = GPIO_PIN(PORT_B, 11) , .cc_chan = 3 },
133  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
134  .af = GPIO_AF2,
135  .bus = APB1
136  },
137  {
138  .dev = TIM3,
139  .rcc_mask = RCC_APB1ENR_TIM3EN,
140  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
141  { .pin = GPIO_PIN(PORT_B, 5) /* D4 */, .cc_chan = 1 },
142  { .pin = GPIO_UNDEF, .cc_chan = 0 },
143  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
144  .af = GPIO_AF1,
145  .bus = APB1
146  },
147  {
148  .dev = TIM15,
149  .rcc_mask = RCC_APB2ENR_TIM15EN,
150  .chan = { { .pin = GPIO_PIN(PORT_B, 14), .cc_chan = 0 },
151  { .pin = GPIO_PIN(PORT_B, 15), .cc_chan = 1 },
152  { .pin = GPIO_UNDEF, .cc_chan = 0 },
153  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
154  .af = GPIO_AF1,
155  .bus = APB2
156  }
157 };
158 
159 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
160 
169 static const uint8_t spi_divtable[2][5] = {
170  { /* for APB1 @ 48000000Hz */
171  7, /* -> 187500Hz */
172  6, /* -> 375000Hz */
173  5, /* -> 750000Hz */
174  2, /* -> 6000000Hz */
175  1 /* -> 12000000Hz */
176  },
177  { /* for APB2 @ 48000000Hz */
178  7, /* -> 187500Hz */
179  6, /* -> 375000Hz */
180  5, /* -> 750000Hz */
181  2, /* -> 6000000Hz */
182  1 /* -> 12000000Hz */
183  }
184 };
185 
186 static const spi_conf_t spi_config[] = {
187  {
188  .dev = SPI1,
189  .mosi_pin = GPIO_PIN(PORT_A, 7),
190  .miso_pin = GPIO_PIN(PORT_A, 6),
191  .sclk_pin = GPIO_PIN(PORT_A, 5),
192  .cs_pin = GPIO_PIN(PORT_A, 4),
193  .af = GPIO_AF0,
194  .rccmask = RCC_APB2ENR_SPI1EN,
195  .apbbus = APB2
196  }
197 };
198 
199 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
200 
206 #define ADC_CONFIG { \
207  { GPIO_PIN(PORT_A, 0), 0 }, \
208  { GPIO_PIN(PORT_A, 1), 1 }, \
209  { GPIO_PIN(PORT_A, 4), 4 }, \
210  { GPIO_PIN(PORT_B, 0), 8 }, \
211  { GPIO_PIN(PORT_C, 1), 11 },\
212  { GPIO_PIN(PORT_C, 0), 10 } \
213 }
214 
215 #define ADC_NUMOF (6)
216 
227 #define RTC_NUMOF (1U)
228 
230 #ifdef __cplusplus
231 }
232 #endif
233 
234 #endif /* PERIPH_CONF_H */
235 
void * dev
UART, USART or LEUART device used.
TIMER_TypeDef * dev
TIMER device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1
PWM device configuration.
NRF_TIMER_Type * dev
timer device
use alternate function 0
UART device configuration.
#define GPIO_UNDEF
Define custom value to speficy undefined or unused GPIOs.
SPI module configuration options.
Timer configuration.
use alternate function 2
cc2538_ssi_t * dev
SSI device.