boards/nucleo-f072/include/periph_conf.h
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1 /*
2  * Copyright (C) 2015 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
20 #ifndef PERIPH_CONF_H
21 #define PERIPH_CONF_H
22 
23 #include "periph_cpu.h"
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
36 /* give the target core clock (HCLK) frequency [in Hz],
37  * maximum: 48MHz */
38  #define CLOCK_CORECLOCK (48000000U)
39  /* 0: no external high speed crystal available
40  * else: actual crystal frequency [in Hz] */
41  #define CLOCK_HSE (8000000U)
42  /* 0: no external low speed crystal available,
43  * 1: external crystal available (always 32.768kHz) */
44  #define CLOCK_LSE (1)
45  /* peripheral clock setup */
46  #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
47  #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
48  #define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
49  #define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
50  #define CLOCK_APB2 (CLOCK_APB1)
51 
52  /* PLL factors */
53  #define CLOCK_PLL_PREDIV (1)
54  #define CLOCK_PLL_MUL (6)
55 
61 static const timer_conf_t timer_config[] = {
62  {
63  .dev = TIM1,
64  .max = 0x0000ffff,
65  .rcc_mask = RCC_APB2ENR_TIM1EN,
66  .bus = APB2,
67  .irqn = TIM1_CC_IRQn
68  }
69 };
70 
71 #define TIMER_0_ISR isr_tim1_cc
72 
73 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
74 
80 static const uart_conf_t uart_config[] = {
81  {
82  .dev = USART2,
83  .rcc_mask = RCC_APB1ENR_USART2EN,
84  .rx_pin = GPIO_PIN(PORT_A, 3),
85  .tx_pin = GPIO_PIN(PORT_A, 2),
86  .rx_af = GPIO_AF1,
87  .tx_af = GPIO_AF1,
88  .bus = APB1,
89  .irqn = USART2_IRQn
90  },
91  {
92  .dev = USART1,
93  .rcc_mask = RCC_APB2ENR_USART1EN,
94  .rx_pin = GPIO_PIN(PORT_A, 10),
95  .tx_pin = GPIO_PIN(PORT_A, 9),
96  .rx_af = GPIO_AF1,
97  .tx_af = GPIO_AF1,
98  .bus = APB2,
99  .irqn = USART1_IRQn
100  },
101  {
102  .dev = USART3,
103  .rcc_mask = RCC_APB1ENR_USART3EN,
104  .rx_pin = GPIO_PIN(PORT_C, 11),
105  .tx_pin = GPIO_PIN(PORT_C, 10),
106  .rx_af = GPIO_AF1,
107  .tx_af = GPIO_AF1,
108  .bus = APB1,
109  .irqn = USART3_8_IRQn
110  }
111 };
112 
113 #define UART_0_ISR (isr_usart2)
114 #define UART_1_ISR (isr_usart1)
115 #define UART_2_ISR (isr_usart3_8)
116 
117 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
118 
124 static const pwm_conf_t pwm_config[] = {
125  {
126  .dev = TIM2,
127  .rcc_mask = RCC_APB1ENR_TIM2EN,
128  .chan = { { .pin = GPIO_PIN(PORT_B, 3) /* D3 */, .cc_chan = 1 },
129  { .pin = GPIO_PIN(PORT_B, 10) /* D6 */, .cc_chan = 2 },
130  { .pin = GPIO_PIN(PORT_B, 11) , .cc_chan = 3 },
131  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
132  .af = GPIO_AF2,
133  .bus = APB1
134  },
135  {
136  .dev = TIM3,
137  .rcc_mask = RCC_APB1ENR_TIM3EN,
138  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
139  { .pin = GPIO_PIN(PORT_B, 5) /* D4 */, .cc_chan = 1 },
140  { .pin = GPIO_UNDEF, .cc_chan = 0 },
141  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
142  .af = GPIO_AF1,
143  .bus = APB1
144  },
145  {
146  .dev = TIM15,
147  .rcc_mask = RCC_APB2ENR_TIM15EN,
148  .chan = { { .pin = GPIO_PIN(PORT_B, 14), .cc_chan = 0 },
149  { .pin = GPIO_PIN(PORT_B, 15), .cc_chan = 1 },
150  { .pin = GPIO_UNDEF, .cc_chan = 0 },
151  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
152  .af = GPIO_AF1,
153  .bus = APB2
154  }
155 };
156 
157 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
158 
167 static const uint8_t spi_divtable[2][5] = {
168  { /* for APB1 @ 48000000Hz */
169  7, /* -> 187500Hz */
170  6, /* -> 375000Hz */
171  5, /* -> 750000Hz */
172  2, /* -> 6000000Hz */
173  1 /* -> 12000000Hz */
174  },
175  { /* for APB2 @ 48000000Hz */
176  7, /* -> 187500Hz */
177  6, /* -> 375000Hz */
178  5, /* -> 750000Hz */
179  2, /* -> 6000000Hz */
180  1 /* -> 12000000Hz */
181  }
182 };
183 
184 static const spi_conf_t spi_config[] = {
185  {
186  .dev = SPI1,
187  .mosi_pin = GPIO_PIN(PORT_A, 7),
188  .miso_pin = GPIO_PIN(PORT_A, 6),
189  .sclk_pin = GPIO_PIN(PORT_A, 5),
190  .cs_pin = GPIO_PIN(PORT_A, 4),
191  .af = GPIO_AF0,
192  .rccmask = RCC_APB2ENR_SPI1EN,
193  .apbbus = APB2
194  }
195 };
196 
197 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
198 
204 #define ADC_CONFIG { \
205  { GPIO_PIN(PORT_A, 0), 0 }, \
206  { GPIO_PIN(PORT_A, 1), 1 }, \
207  { GPIO_PIN(PORT_A, 4), 4 }, \
208  { GPIO_PIN(PORT_B, 0), 8 }, \
209  { GPIO_PIN(PORT_C, 1), 11 },\
210  { GPIO_PIN(PORT_C, 0), 10 } \
211 }
212 
213 #define ADC_NUMOF (6)
214 
225 #define RTC_NUMOF (1U)
226 
228 #ifdef __cplusplus
229 }
230 #endif
231 
232 #endif /* PERIPH_CONF_H */
233 
void * dev
UART, USART or LEUART device used.
TIMER_TypeDef * dev
TIMER device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1
PWM device configuration.
NRF_TIMER_Type * dev
timer device
use alternate function 0
UART device configuration.
#define GPIO_UNDEF
Define custom value to speficy undefined or unused GPIOs.
SPI module configuration options.
Timer configuration.
use alternate function 2
cc2538_ssi_t * dev
SSI device.