Loading...
Searching...
No Matches
periph_conf.h
Go to the documentation of this file.
1/*
2 * Copyright (C) 2016 Freie Universität Berlin
3 * 2016 Inria
4 *
5 * This file is subject to the terms and conditions of the GNU Lesser
6 * General Public License v2.1. See the file LICENSE in the top level
7 * directory for more details.
8 */
9
21#ifndef PERIPH_CONF_H
22#define PERIPH_CONF_H
23
24/* HSE available on this board */
25#ifndef CONFIG_BOARD_HAS_HSE
26#define CONFIG_BOARD_HAS_HSE 1
27#endif
28
29/* This board provides an LSE */
30#ifndef CONFIG_BOARD_HAS_LSE
31#define CONFIG_BOARD_HAS_LSE 1
32#endif
33
34#include "periph_cpu.h"
35#include "clk_conf.h"
36#include "cfg_i2c1_pb8_pb9.h"
37
38#ifdef __cplusplus
39extern "C" {
40#endif
41
46static const timer_conf_t timer_config[] = {
47 {
48 .dev = TIM1,
49 .max = 0x0000ffff,
50 .rcc_mask = RCC_APB2ENR_TIM1EN,
51 .bus = APB2,
52 .irqn = TIM1_CC_IRQn
53 }
54};
55
56#define TIMER_0_ISR isr_tim1_cc
57
58#define TIMER_NUMOF ARRAY_SIZE(timer_config)
65static const uart_conf_t uart_config[] = {
66 {
67 .dev = USART2,
68 .rcc_mask = RCC_APB1ENR_USART2EN,
69 .rx_pin = GPIO_PIN(PORT_A, 3),
70 .tx_pin = GPIO_PIN(PORT_A, 2),
71 .rx_af = GPIO_AF1,
72 .tx_af = GPIO_AF1,
73 .bus = APB1,
74 .irqn = USART2_IRQn
75 },
76 {
77 .dev = USART1,
78 .rcc_mask = RCC_APB2ENR_USART1EN,
79 .rx_pin = GPIO_PIN(PORT_A, 10),
80 .tx_pin = GPIO_PIN(PORT_A, 9),
81 .rx_af = GPIO_AF1,
82 .tx_af = GPIO_AF1,
83 .bus = APB2,
84 .irqn = USART1_IRQn
85 },
86 {
87 .dev = USART3,
88 .rcc_mask = RCC_APB1ENR_USART3EN,
89 .rx_pin = GPIO_PIN(PORT_C, 11),
90 .tx_pin = GPIO_PIN(PORT_C, 10),
91 .rx_af = GPIO_AF1,
92 .tx_af = GPIO_AF1,
93 .bus = APB1,
94 .irqn = USART3_4_IRQn
95 }
96};
97
98#define UART_0_ISR (isr_usart2)
99#define UART_1_ISR (isr_usart1)
100#define UART_2_ISR (isr_usart3_8)
101
102#define UART_NUMOF ARRAY_SIZE(uart_config)
109static const dma_conf_t dma_config[] = {
110 { .stream = 1 },
111 { .stream = 2 },
112};
113
114#define DMA_SHARED_ISR_0 isr_dma1_ch2_3_dma2_ch1_2
115#define DMA_SHARED_ISR_0_STREAMS { 0, 1 } /* Indexes 0 and 1 of dma_config share the same isr */
116
117#define DMA_NUMOF ARRAY_SIZE(dma_config)
124static const pwm_conf_t pwm_config[] = {
125 {
126 .dev = TIM3,
127 .rcc_mask = RCC_APB1ENR_TIM3EN,
128 .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
129 { .pin = GPIO_PIN(PORT_B, 5) /* D4 */, .cc_chan = 1 },
130 { .pin = GPIO_UNDEF, .cc_chan = 0 },
131 { .pin = GPIO_UNDEF, .cc_chan = 0 } },
132 .af = GPIO_AF1,
133 .bus = APB1
134 },
135 {
136 .dev = TIM15,
137 .rcc_mask = RCC_APB2ENR_TIM15EN,
138 .chan = { { .pin = GPIO_PIN(PORT_B, 14), .cc_chan = 0 },
139 { .pin = GPIO_PIN(PORT_B, 15), .cc_chan = 1 },
140 { .pin = GPIO_UNDEF, .cc_chan = 0 },
141 { .pin = GPIO_UNDEF, .cc_chan = 0 } },
142 .af = GPIO_AF1,
143 .bus = APB2
144 }
145};
146
147#define PWM_NUMOF ARRAY_SIZE(pwm_config)
154static const adc_conf_t adc_config[] = {
155 { GPIO_PIN(PORT_A, 0), 0 },
156 { GPIO_PIN(PORT_A, 1), 1 },
157 { GPIO_PIN(PORT_A, 4), 4 },
158 { GPIO_PIN(PORT_B, 0), 8 },
159 { GPIO_PIN(PORT_C, 1), 11 },
160 { GPIO_PIN(PORT_C, 0), 10 }
161};
162
163#define ADC_NUMOF ARRAY_SIZE(adc_config)
177static const spi_conf_t spi_config[] = {
178 {
179 .dev = SPI1,
180 .mosi_pin = GPIO_PIN(PORT_A, 7),
181 .miso_pin = GPIO_PIN(PORT_A, 6),
182 .sclk_pin = GPIO_PIN(PORT_A, 5),
183 .cs_pin = GPIO_UNDEF,
184 .mosi_af = GPIO_AF0,
185 .miso_af = GPIO_AF0,
186 .sclk_af = GPIO_AF0,
187 .cs_af = GPIO_AF0,
188 .rccmask = RCC_APB2ENR_SPI1EN,
189 .apbbus = APB2,
190#ifdef MODULE_PERIPH_DMA
191 .tx_dma = 1,
192 .tx_dma_chan = 0,
193 .rx_dma = 0,
194 .rx_dma_chan = 0,
195#endif
196 }
197};
198
199#define SPI_NUMOF ARRAY_SIZE(spi_config)
202#ifdef __cplusplus
203}
204#endif
205
206#endif /* PERIPH_CONF_H */
@ PORT_B
port B
Definition periph_cpu.h:48
@ PORT_C
port C
Definition periph_cpu.h:49
@ PORT_A
port A
Definition periph_cpu.h:47
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Common configuration for STM32 I2C.
@ GPIO_AF1
use alternate function 1
Definition cpu_gpio.h:103
@ GPIO_AF0
use alternate function 0
Definition cpu_gpio.h:102
@ APB1
Advanced Peripheral Bus 1
Definition periph_cpu.h:79
@ APB2
Advanced Peripheral Bus 2
Definition periph_cpu.h:80
ADC device configuration.
Definition periph_cpu.h:379
DMA configuration.
Definition cpu_dma.h:32
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition cpu_dma.h:55
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:338
Timer device configuration.
Definition periph_cpu.h:264
TC0_t * dev
Pointer to the used as Timer device.
Definition periph_cpu.h:265
UART device configuration.
Definition periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:219