boards/nucleo-f070/include/periph_conf.h
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1 /*
2  * Copyright (C) 2016 Freie Universit├Ąt Berlin
3  * 2016 Inria
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 #include "periph_cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
37 /* give the target core clock (HCLK) frequency [in Hz],
38  * maximum: 48MHz */
39  #define CLOCK_CORECLOCK (48000000U)
40  /* 0: no external high speed crystal available
41  * else: actual crystal frequency [in Hz] */
42  #define CLOCK_HSE (8000000U)
43  /* 0: no external low speed crystal available,
44  * 1: external crystal available (always 32.768kHz) */
45  #define CLOCK_LSE (1)
46  /* peripheral clock setup */
47  #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
48  #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
49  #define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
50  #define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
51  #define CLOCK_APB2 (CLOCK_APB1)
52 
53  /* PLL factors */
54  #define CLOCK_PLL_PREDIV (1)
55  #define CLOCK_PLL_MUL (6)
56 
62 static const timer_conf_t timer_config[] = {
63  {
64  .dev = TIM1,
65  .max = 0x0000ffff,
66  .rcc_mask = RCC_APB2ENR_TIM1EN,
67  .bus = APB2,
68  .irqn = TIM1_CC_IRQn
69  }
70 };
71 
72 #define TIMER_0_ISR isr_tim1_cc
73 
74 
75 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
76 
82 static const uart_conf_t uart_config[] = {
83  {
84  .dev = USART2,
85  .rcc_mask = RCC_APB1ENR_USART2EN,
86  .rx_pin = GPIO_PIN(PORT_A, 3),
87  .tx_pin = GPIO_PIN(PORT_A, 2),
88  .rx_af = GPIO_AF1,
89  .tx_af = GPIO_AF1,
90  .bus = APB1,
91  .irqn = USART2_IRQn
92  },
93  {
94  .dev = USART1,
95  .rcc_mask = RCC_APB2ENR_USART1EN,
96  .rx_pin = GPIO_PIN(PORT_A, 10),
97  .tx_pin = GPIO_PIN(PORT_A, 9),
98  .rx_af = GPIO_AF1,
99  .tx_af = GPIO_AF1,
100  .bus = APB2,
101  .irqn = USART1_IRQn
102  },
103  {
104  .dev = USART3,
105  .rcc_mask = RCC_APB1ENR_USART3EN,
106  .rx_pin = GPIO_PIN(PORT_C, 11),
107  .tx_pin = GPIO_PIN(PORT_C, 10),
108  .rx_af = GPIO_AF1,
109  .tx_af = GPIO_AF1,
110  .bus = APB1,
111  .irqn = USART3_4_IRQn
112  }
113 };
114 
115 #define UART_0_ISR (isr_usart2)
116 #define UART_1_ISR (isr_usart1)
117 #define UART_2_ISR (isr_usart3_8)
118 
119 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
120 
126 static const pwm_conf_t pwm_config[] = {
127  {
128  .dev = TIM3,
129  .rcc_mask = RCC_APB1ENR_TIM3EN,
130  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
131  { .pin = GPIO_PIN(PORT_B, 5) /* D4 */, .cc_chan = 1 },
132  { .pin = GPIO_UNDEF, .cc_chan = 0 },
133  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
134  .af = GPIO_AF1,
135  .bus = APB1
136  },
137  {
138  .dev = TIM15,
139  .rcc_mask = RCC_APB2ENR_TIM15EN,
140  .chan = { { .pin = GPIO_PIN(PORT_B, 14), .cc_chan = 0 },
141  { .pin = GPIO_PIN(PORT_B, 15), .cc_chan = 1 },
142  { .pin = GPIO_UNDEF, .cc_chan = 0 },
143  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
144  .af = GPIO_AF1,
145  .bus = APB2
146  }
147 };
148 
149 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
150 
156 #define ADC_CONFIG { \
157  { GPIO_PIN(PORT_A, 0), 0 },\
158  { GPIO_PIN(PORT_A, 1), 1 },\
159  { GPIO_PIN(PORT_A, 4), 4 },\
160  { GPIO_PIN(PORT_B, 0), 8 },\
161  { GPIO_PIN(PORT_C, 1), 11 },\
162  { GPIO_PIN(PORT_C, 0), 10 } \
163 }
164 
165 #define ADC_NUMOF (6)
166 
177 #define RTC_NUMOF (1U)
178 
180 #ifdef __cplusplus
181 }
182 #endif
183 
184 #endif /* PERIPH_CONF_H */
185 
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1
PWM configuration structure.
NRF_TIMER_Type * dev
timer device
Tcc * dev
TCC device to use.
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
Timer configuration.