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boards/nucleo-f070/include/periph_conf.h
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1 /*
2  * Copyright (C) 2016 Freie Universit├Ąt Berlin
3  * 2016 Inria
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 #include "periph_cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
34 #define CLOCK_HSE (8000000U) /* external oscillator */
35 #define CLOCK_CORECLOCK (48000000U) /* desired core clock frequency */
36 
37 /* the actual PLL values are automatically generated */
38 #define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE)
39 
40 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
41 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
42 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
43 #define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
44 
50 static const timer_conf_t timer_config[] = {
51  {
52  .dev = TIM1,
53  .max = 0x0000ffff,
54  .rcc_mask = RCC_APB2ENR_TIM1EN,
55  .bus = APB2,
56  .irqn = TIM1_CC_IRQn
57  }
58 };
59 
60 #define TIMER_0_ISR isr_tim1_cc
61 
62 
63 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
64 
70 static const uart_conf_t uart_config[] = {
71  {
72  .dev = USART2,
73  .rcc_mask = RCC_APB1ENR_USART2EN,
74  .rx_pin = GPIO_PIN(PORT_A, 3),
75  .tx_pin = GPIO_PIN(PORT_A, 2),
76  .rx_af = GPIO_AF1,
77  .tx_af = GPIO_AF1,
78  .bus = APB1,
79  .irqn = USART2_IRQn
80  },
81  {
82  .dev = USART1,
83  .rcc_mask = RCC_APB2ENR_USART1EN,
84  .rx_pin = GPIO_PIN(PORT_A, 10),
85  .tx_pin = GPIO_PIN(PORT_A, 9),
86  .rx_af = GPIO_AF1,
87  .tx_af = GPIO_AF1,
88  .bus = APB2,
89  .irqn = USART1_IRQn
90  },
91  {
92  .dev = USART3,
93  .rcc_mask = RCC_APB1ENR_USART3EN,
94  .rx_pin = GPIO_PIN(PORT_C, 11),
95  .tx_pin = GPIO_PIN(PORT_C, 10),
96  .rx_af = GPIO_AF1,
97  .tx_af = GPIO_AF1,
98  .bus = APB1,
99  .irqn = USART3_4_IRQn
100  }
101 };
102 
103 #define UART_0_ISR (isr_usart2)
104 #define UART_1_ISR (isr_usart1)
105 #define UART_2_ISR (isr_usart3_8)
106 
107 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
108 
114 static const pwm_conf_t pwm_config[] = {
115  {
116  .dev = TIM3,
117  .rcc_mask = RCC_APB1ENR_TIM3EN,
118  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
119  { .pin = GPIO_PIN(PORT_B, 5) /* D4 */, .cc_chan = 1 },
120  { .pin = GPIO_UNDEF, .cc_chan = 0 },
121  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
122  .af = GPIO_AF1,
123  .bus = APB1
124  },
125  {
126  .dev = TIM15,
127  .rcc_mask = RCC_APB2ENR_TIM15EN,
128  .chan = { { .pin = GPIO_PIN(PORT_B, 14), .cc_chan = 0 },
129  { .pin = GPIO_PIN(PORT_B, 15), .cc_chan = 1 },
130  { .pin = GPIO_UNDEF, .cc_chan = 0 },
131  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
132  .af = GPIO_AF1,
133  .bus = APB2
134  }
135 };
136 
137 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
138 
144 #define ADC_CONFIG { \
145  { GPIO_PIN(PORT_A, 0), 0 },\
146  { GPIO_PIN(PORT_A, 1), 1 },\
147  { GPIO_PIN(PORT_A, 4), 4 },\
148  { GPIO_PIN(PORT_B, 0), 8 },\
149  { GPIO_PIN(PORT_C, 1), 11 },\
150  { GPIO_PIN(PORT_C, 0), 10 } \
151 }
152 
153 #define ADC_NUMOF (6)
154 
160 #define DAC_NUMOF (0)
161 
172 #define RTC_NUMOF (1U)
173 
175 #ifdef __cplusplus
176 }
177 #endif
178 
179 #endif /* PERIPH_CONF_H */
180 
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1
PWM configuration structure.
LPC_CTxxBx_Type * dev
PWM device.
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
cc2538_gptimer_t * dev
timer device
Timer configuration data.