boards/nucleo-f030/include/periph_conf.h
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1 /*
2  * Copyright (C) 2016 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 #include "periph_cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
37 /* give the target core clock (HCLK) frequency [in Hz],
38  * maximum: 48MHz */
39  #define CLOCK_CORECLOCK (48000000U)
40  /* 0: no external high speed crystal available
41  * else: actual crystal frequency [in Hz] */
42  #define CLOCK_HSE (8000000U)
43  /* 0: no external low speed crystal available,
44  * 1: external crystal available (always 32.768kHz) */
45  #define CLOCK_LSE (1)
46  /* peripheral clock setup */
47  #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
48  #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
49  #define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
50  #define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
51  #define CLOCK_APB2 (CLOCK_APB1)
52 
53  /* PLL factors */
54  #define CLOCK_PLL_PREDIV (1)
55  #define CLOCK_PLL_MUL (6)
56 
62 static const timer_conf_t timer_config[] = {
63  {
64  .dev = TIM1,
65  .max = 0x0000ffff,
66  .rcc_mask = RCC_APB2ENR_TIM1EN,
67  .bus = APB2,
68  .irqn = TIM1_CC_IRQn
69  }
70 };
71 
72 #define TIMER_0_ISR (isr_tim1_cc)
73 
74 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
75 
81 static const uart_conf_t uart_config[] = {
82  {
83  .dev = USART2,
84  .rcc_mask = RCC_APB1ENR_USART2EN,
85  .rx_pin = GPIO_PIN(PORT_A, 3),
86  .tx_pin = GPIO_PIN(PORT_A, 2),
87  .rx_af = GPIO_AF1,
88  .tx_af = GPIO_AF1,
89  .bus = APB1,
90  .irqn = USART2_IRQn
91  },
92  {
93  .dev = USART1,
94  .rcc_mask = RCC_APB2ENR_USART1EN,
95  .rx_pin = GPIO_PIN(PORT_A, 10),
96  .tx_pin = GPIO_PIN(PORT_A, 9),
97  .rx_af = GPIO_AF1,
98  .tx_af = GPIO_AF1,
99  .bus = APB2,
100  .irqn = USART1_IRQn
101  }
102 };
103 
104 #define UART_0_ISR (isr_usart2)
105 #define UART_1_ISR (isr_usart1)
106 
107 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
108 
114 static const pwm_conf_t pwm_config[] = {
115  {
116  .dev = TIM3,
117  .rcc_mask = RCC_APB1ENR_TIM3EN,
118  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0},
119  { .pin = GPIO_PIN(PORT_B, 5) /* D4 */, .cc_chan = 1},
120  { .pin = GPIO_UNDEF, .cc_chan = 0},
121  { .pin = GPIO_UNDEF, .cc_chan = 0} },
122  .af = GPIO_AF1,
123  .bus = APB1
124  },
125  {
126  .dev = TIM15,
127  .rcc_mask = RCC_APB2ENR_TIM15EN,
128  .chan = { { .pin = GPIO_PIN(PORT_B, 14), .cc_chan = 0},
129  { .pin = GPIO_PIN(PORT_B, 15), .cc_chan = 1},
130  { .pin = GPIO_UNDEF, .cc_chan = 0},
131  { .pin = GPIO_UNDEF, .cc_chan = 0} },
132  .af = GPIO_AF1,
133  .bus = APB2
134  }
135 };
136 
137 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
138 
144 #define ADC_CONFIG { \
145  { GPIO_PIN(PORT_A, 0), 0 }, \
146  { GPIO_PIN(PORT_A, 1), 1 }, \
147  { GPIO_PIN(PORT_A, 4), 4 }, \
148  { GPIO_PIN(PORT_B, 0), 8 }, \
149  { GPIO_PIN(PORT_C, 1), 11 },\
150  { GPIO_PIN(PORT_C, 0), 10 } \
151 }
152 
153 #define ADC_NUMOF (6)
154 
165 #define RTC_NUMOF (1U)
166 
168 #ifdef __cplusplus
169 }
170 #endif
171 
172 #endif /* PERIPH_CONF_H */
173 
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1
PWM configuration structure.
NRF_TIMER_Type * dev
timer device
Tcc * dev
TCC device to use.
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
Timer configuration.