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boards/nucleo-f030/include/periph_conf.h
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1 /*
2  * Copyright (C) 2016 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 #include "periph_cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
34 #define CLOCK_HSE (8000000U) /* external oscillator */
35 #define CLOCK_CORECLOCK (48000000U) /* desired core clock frequency */
36 
37 /* the actual PLL values are automatically generated */
38 #define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE)
39 
40 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
41 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
42 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
43 #define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
44 
50 static const timer_conf_t timer_config[] = {
51  {
52  .dev = TIM1,
53  .max = 0x0000ffff,
54  .rcc_mask = RCC_APB2ENR_TIM1EN,
55  .bus = APB2,
56  .irqn = TIM1_CC_IRQn
57  }
58 };
59 
60 #define TIMER_0_ISR (isr_tim1_cc)
61 
62 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
63 
69 static const uart_conf_t uart_config[] = {
70  {
71  .dev = USART2,
72  .rcc_mask = RCC_APB1ENR_USART2EN,
73  .rx_pin = GPIO_PIN(PORT_A, 3),
74  .tx_pin = GPIO_PIN(PORT_A, 2),
75  .rx_af = GPIO_AF1,
76  .tx_af = GPIO_AF1,
77  .bus = APB1,
78  .irqn = USART2_IRQn
79  },
80  {
81  .dev = USART1,
82  .rcc_mask = RCC_APB2ENR_USART1EN,
83  .rx_pin = GPIO_PIN(PORT_A, 10),
84  .tx_pin = GPIO_PIN(PORT_A, 9),
85  .rx_af = GPIO_AF1,
86  .tx_af = GPIO_AF1,
87  .bus = APB2,
88  .irqn = USART1_IRQn
89  }
90 };
91 
92 #define UART_0_ISR (isr_usart2)
93 #define UART_1_ISR (isr_usart1)
94 
95 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
96 
102 static const pwm_conf_t pwm_config[] = {
103  {
104  .dev = TIM3,
105  .rcc_mask = RCC_APB1ENR_TIM3EN,
106  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0},
107  { .pin = GPIO_PIN(PORT_B, 5) /* D4 */, .cc_chan = 1},
108  { .pin = GPIO_UNDEF, .cc_chan = 0},
109  { .pin = GPIO_UNDEF, .cc_chan = 0} },
110  .af = GPIO_AF1,
111  .bus = APB1
112  },
113  {
114  .dev = TIM15,
115  .rcc_mask = RCC_APB2ENR_TIM15EN,
116  .chan = { { .pin = GPIO_PIN(PORT_B, 14), .cc_chan = 0},
117  { .pin = GPIO_PIN(PORT_B, 15), .cc_chan = 1},
118  { .pin = GPIO_UNDEF, .cc_chan = 0},
119  { .pin = GPIO_UNDEF, .cc_chan = 0} },
120  .af = GPIO_AF1,
121  .bus = APB2
122  }
123 };
124 
125 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
126 
132 #define ADC_CONFIG { \
133  { GPIO_PIN(PORT_A, 0), 0 }, \
134  { GPIO_PIN(PORT_A, 1), 1 }, \
135  { GPIO_PIN(PORT_A, 4), 4 }, \
136  { GPIO_PIN(PORT_B, 0), 8 }, \
137  { GPIO_PIN(PORT_C, 1), 11 },\
138  { GPIO_PIN(PORT_C, 0), 10 } \
139 }
140 
141 #define ADC_NUMOF (6)
142 
148 #define DAC_NUMOF (0)
149 
160 #define RTC_NUMOF (1U)
161 
163 #ifdef __cplusplus
164 }
165 #endif
166 
167 #endif /* PERIPH_CONF_H */
168 
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1
PWM configuration structure.
LPC_CTxxBx_Type * dev
PWM device.
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
cc2538_gptimer_t * dev
timer device
Timer configuration data.