boards/mulle/include/periph_conf.h
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1 /*
2  * Copyright (C) 2015 Eistec AB
3  * 2016 Freie Universit├Ąt Berlin
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser General
6  * Public License v2.1. See the file LICENSE in the top level directory for more
7  * details.
8  */
9 
10 
22 #ifndef PERIPH_CONF_H
23 #define PERIPH_CONF_H
24 
25 #include "periph_cpu.h"
26 
27 #ifdef __cplusplus
28 extern "C"
29 {
30 #endif
31 
36 #define KINETIS_CPU_USE_MCG 1
37 
38 #define KINETIS_MCG_USE_ERC 1
39 #define KINETIS_MCG_USE_PLL 0
40 #define KINETIS_MCG_DCO_RANGE (96000000U)
41 #define KINETIS_MCG_ERC_OSCILLATOR 0
42 #define KINETIS_MCG_ERC_FRDIV 0
43 #define KINETIS_MCG_ERC_RANGE 0
44 #define KINETIS_MCG_ERC_FREQ (32768U)
45 
47 #define CPU_XTAL_CLK_HZ 8000000u
48 
49 #define CPU_XTAL32k_CLK_HZ 32768u
50 
51 #define CPU_INT_SLOW_CLK_HZ 32768u
52 
53 #define CPU_INT_FAST_CLK_HZ 4000000u
54 
55 #define DEFAULT_SYSTEM_CLOCK (CPU_XTAL32k_CLK_HZ * 2929u)
56 
57 /* bus clock for the peripherals */
58 #define CLOCK_CORECLOCK (DEFAULT_SYSTEM_CLOCK)
59 #define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 2)
60 
66 #define PIT_NUMOF (2U)
67 #define PIT_CONFIG { \
68  { \
69  .prescaler_ch = 0, \
70  .count_ch = 1, \
71  }, \
72  { \
73  .prescaler_ch = 2, \
74  .count_ch = 3, \
75  }, \
76  }
77 #define LPTMR_NUMOF (1U)
78 #define LPTMR_CONFIG { \
79  { \
80  .dev = LPTMR0, \
81  .irqn = LPTMR0_IRQn, \
82  } \
83  }
84 #define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
85 
86 #define PIT_BASECLOCK (CLOCK_BUSCLOCK)
87 #define PIT_ISR_0 isr_pit1
88 #define PIT_ISR_1 isr_pit3
89 #define LPTMR_ISR_0 isr_lptmr0
90 
97 static const uart_conf_t uart_config[] = {
98  {
99  .dev = UART0,
100  .freq = CLOCK_CORECLOCK,
101  .pin_rx = GPIO_PIN(PORT_A, 14),
102  .pin_tx = GPIO_PIN(PORT_A, 15),
103  .pcr_rx = PORT_PCR_MUX(3),
104  .pcr_tx = PORT_PCR_MUX(3),
105  .irqn = UART0_RX_TX_IRQn,
106  .scgc_addr = &SIM->SCGC4,
107  .scgc_bit = SIM_SCGC4_UART0_SHIFT,
108  .mode = UART_MODE_8N1
109  },
110  {
111  .dev = UART1,
112  .freq = CLOCK_CORECLOCK,
113  .pin_rx = GPIO_PIN(PORT_C, 3),
114  .pin_tx = GPIO_PIN(PORT_C, 4),
115  .pcr_rx = PORT_PCR_MUX(3),
116  .pcr_tx = PORT_PCR_MUX(3),
117  .irqn = UART1_RX_TX_IRQn,
118  .scgc_addr = &SIM->SCGC4,
119  .scgc_bit = SIM_SCGC4_UART1_SHIFT,
120  .mode = UART_MODE_8N1
121  },
122 };
123 
124 #define UART_0_ISR (isr_uart0_rx_tx)
125 #define UART_1_ISR (isr_uart1_rx_tx)
126 
127 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
128 
134 static const adc_conf_t adc_config[] = {
135  /* dev, pin, channel */
136  [ 0] = { ADC1, GPIO_UNDEF, 26 }, /* internal: temperature sensor */
137  [ 1] = { ADC1, GPIO_UNDEF, 27 }, /* internal: band gap */
138  [ 2] = { ADC1, GPIO_UNDEF, 29 }, /* internal: V_REFSH */
139  [ 3] = { ADC1, GPIO_UNDEF, 30 }, /* internal: V_REFSL */
140  [ 4] = { ADC1, GPIO_UNDEF, 23 }, /* internal: DAC0 module output level */
141  [ 5] = { ADC1, GPIO_UNDEF, 18 }, /* internal: VREF module output level */
142  [ 6] = { ADC1, GPIO_UNDEF, 0 }, /* on board connection to Mulle Vbat/2 on PGA1_DP pin */
143  [ 7] = { ADC1, GPIO_UNDEF, 19 }, /* on board connection to Mulle Vchr/2 on PGA1_DM pin */
144  [ 8] = { ADC0, GPIO_UNDEF, 0 }, /* expansion port PGA0_DP pin */
145  [ 9] = { ADC0, GPIO_UNDEF, 19 }, /* expansion port PGA0_DM pin */
146  [10] = { ADC1, GPIO_PIN(PORT_A, 17), 17 }, /* expansion port PTA17 */
147  [11] = { ADC1, GPIO_PIN(PORT_B, 0), 8 }, /* expansion port PTB0 */
148  [12] = { ADC0, GPIO_PIN(PORT_C, 0), 14 }, /* expansion port PTC0 */
149  [13] = { ADC1, GPIO_PIN(PORT_C, 8), 4 }, /* expansion port PTC8 */
150  [14] = { ADC1, GPIO_PIN(PORT_C, 9), 5 }, /* expansion port PTC9 */
151  [15] = { ADC1, GPIO_PIN(PORT_C, 10), 6 }, /* expansion port PTC10 */
152  [16] = { ADC1, GPIO_PIN(PORT_C, 11), 7 }, /* expansion port PTC11 */
153 };
154 
155 #define ADC_NUMOF (sizeof(adc_config) / sizeof(adc_config[0]))
156 
163 #define DAC_CONFIG { \
164  { DAC0, (uint32_t volatile *)BITBAND_REGADDR(SIM->SCGC2, SIM_SCGC2_DAC0_SHIFT) }, \
165  }
166 #define DAC_NUMOF 1
167 
174 static const pwm_conf_t pwm_config[] = {
175  {
176  .ftm = FTM0,
177  .chan = {
178  { .pin = GPIO_PIN(PORT_C, 1), .af = 4, .ftm_chan = 0 },
179  { .pin = GPIO_PIN(PORT_C, 2), .af = 4, .ftm_chan = 1 },
180  { .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 },
181  { .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 }
182  },
183  .chan_numof = 2,
184  .ftm_num = 0
185  },
186  {
187  .ftm = FTM1,
188  .chan = {
189  { .pin = GPIO_PIN(PORT_A, 12), .af = 3, .ftm_chan = 0 },
190  { .pin = GPIO_PIN(PORT_A, 13), .af = 3, .ftm_chan = 1 },
191  { .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 },
192  { .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 }
193  },
194  .chan_numof = 2,
195  .ftm_num = 1
196  }
197 };
198 
199 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
200 
212 static const uint32_t spi_clk_config[] = {
213  (
214  SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | /* -> 93728Hz */
215  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
216  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
217  SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
218  ),
219  (
220  SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | /* -> 374912Hz */
221  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
222  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
223  SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
224  ),
225  (
226  SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | /* -> 999765Hz */
227  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
228  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
229  SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
230  ),
231  (
232  SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | /* -> 4798873Hz */
233  SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
234  SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
235  SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
236  ),
237  (
238  SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 7998122Hz */
239  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
240  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
241  SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
242  )
243 };
244 
245 static const spi_conf_t spi_config[] = {
246  {
247  .dev = SPI0,
248  .pin_miso = GPIO_PIN(PORT_D, 3),
249  .pin_mosi = GPIO_PIN(PORT_D, 2),
250  .pin_clk = GPIO_PIN(PORT_D, 1),
251  .pin_cs = {
252  GPIO_PIN(PORT_D, 0),
253  GPIO_PIN(PORT_D, 4),
254  GPIO_PIN(PORT_D, 5),
255  GPIO_PIN(PORT_D, 6),
256  GPIO_UNDEF
257  },
258  .pcr = GPIO_AF_2,
259  .simmask = SIM_SCGC6_SPI0_MASK
260  },
261  {
262  .dev = SPI1,
263  .pin_miso = GPIO_PIN(PORT_E, 3),
264  .pin_mosi = GPIO_PIN(PORT_E, 1),
265  .pin_clk = GPIO_PIN(PORT_E, 2),
266  .pin_cs = {
267  GPIO_PIN(PORT_E, 4),
268  GPIO_UNDEF,
269  GPIO_UNDEF,
270  GPIO_UNDEF,
271  GPIO_UNDEF
272  },
273  .pcr = GPIO_AF_2,
274  .simmask = SIM_SCGC6_SPI1_MASK
275  }
276 };
277 
278 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
279 
287 #define I2C_NUMOF (1U)
288 #define I2C_CLK CLOCK_BUSCLOCK
289 #define I2C_0_EN 1
290 #define I2C_1_EN 0
291 #define I2C_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
292 
293 /* I2C 0 device configuration */
294 #define I2C_0_DEV I2C0
295 #define I2C_0_CLKEN() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_I2C0_SHIFT) = 1)
296 #define I2C_0_CLKDIS() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_I2C0_SHIFT) = 0)
297 #define I2C_0_IRQ I2C0_IRQn
298 #define I2C_0_IRQ_HANDLER isr_i2c0
299 /* I2C 0 pin configuration */
300 #define I2C_0_PORT PORTB
301 #define I2C_0_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
302 #define I2C_0_PIN_AF 2
303 #define I2C_0_SDA_PIN 1
304 #define I2C_0_SCL_PIN 2
305 #define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
306 
312 /* Low (10 kHz): MUL = 4, SCL divider = 2560, total: 10240 */
313 #define KINETIS_I2C_F_ICR_LOW (0x3D)
314 #define KINETIS_I2C_F_MULT_LOW (2)
315 /* Normal (100 kHz): MUL = 2, SCL divider = 240, total: 480 */
316 #define KINETIS_I2C_F_ICR_NORMAL (0x1F)
317 #define KINETIS_I2C_F_MULT_NORMAL (1)
318 /* Fast (400 kHz): MUL = 1, SCL divider = 128, total: 128 */
319 #define KINETIS_I2C_F_ICR_FAST (0x17)
320 #define KINETIS_I2C_F_MULT_FAST (0)
321 /* Fast plus (1000 kHz): MUL = 1, SCL divider = 48, total: 48 */
322 #define KINETIS_I2C_F_ICR_FAST_PLUS (0x10)
323 #define KINETIS_I2C_F_MULT_FAST_PLUS (0)
324 
330 #define GPIO_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
331 
338 /* RIOT RTC implementation uses RTT for underlying timekeeper */
339 #define RTC_NUMOF (1U)
340 
346 #define RTT_NUMOF (1U)
347 #define RTT_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
348 #define RTT_IRQ RTC_IRQn
349 #define RTT_ISR isr_rtc_alarm
350 #define RTT_DEV RTC
351 #define RTT_UNLOCK() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_RTC_SHIFT) = 1)
352 #define RTT_MAX_VALUE (0xffffffff)
353 #define RTT_FREQUENCY (1) /* in Hz */
354 
358 /* The crystal on the Mulle is designed for 12.5 pF load capacitance. According
359  * to the data sheet, the K60 will have a 5 pF parasitic capacitance on the
360  * XTAL32/EXTAL32 connection. The board traces might give some minor parasitic
361  * capacitance as well. */
362 /* enable 6pF load capacitance, might need adjusting.. */
363 #define RTT_LOAD_CAP_BITS (RTC_CR_SC4P_MASK | RTC_CR_SC2P_MASK | RTC_CR_SC1P_MASK)
364 
371 #define HWRNG_CLKEN() (BITBAND_REG32(SIM->SCGC3, SIM_SCGC3_RNGA_SHIFT) = 1)
372 #define HWRNG_CLKDIS() (BITBAND_REG32(SIM->SCGC3, SIM_SCGC3_RNGA_SHIFT) = 0)
373 
375 #ifdef __cplusplus
376 }
377 #endif
378 
379 #endif /* PERIPH_CONF_H */
380 
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
cc2538_uart_t *const UART0
UART0 Instance.
PWM configuration structure.
use alternate function 2
#define UART_MODE_8N1
8 data bits, no parity, 1 stop bit
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
CPU specific ADC configuration.
cc2538_uart_t *const UART1
UART1 Instance.
cc2538_ssi_t * dev
SSI device.