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boards/mulle/include/periph_conf.h
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1 /*
2  * Copyright (C) 2015 Eistec AB
3  * 2016 Freie Universit├Ąt Berlin
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser General
6  * Public License v2.1. See the file LICENSE in the top level directory for more
7  * details.
8  */
9 
10 
22 #ifndef MULLE_PERIPH_CONF_H
23 #define MULLE_PERIPH_CONF_H
24 
25 #include "periph_cpu.h"
26 
27 #ifdef __cplusplus
28 extern "C"
29 {
30 #endif
31 
36 #define KINETIS_CPU_USE_MCG 1
37 
38 #define KINETIS_MCG_USE_ERC 1
39 #define KINETIS_MCG_USE_PLL 0
40 #define KINETIS_MCG_DCO_RANGE (96000000U)
41 #define KINETIS_MCG_ERC_OSCILLATOR 0
42 #define KINETIS_MCG_ERC_FRDIV 0
43 #define KINETIS_MCG_ERC_RANGE 0
44 #define KINETIS_MCG_ERC_FREQ (32768U)
45 
46 /* Base clocks, used by SystemCoreClockUpdate */
48 #define CPU_XTAL_CLK_HZ 8000000u
49 
50 #define CPU_XTAL32k_CLK_HZ 32768u
51 
52 #define CPU_INT_SLOW_CLK_HZ 32768u
53 
54 #define CPU_INT_FAST_CLK_HZ 4000000u
55 
56 #define DEFAULT_SYSTEM_CLOCK (CPU_XTAL32k_CLK_HZ * 2929u)
57 
58 /* bus clock for the peripherals */
59 #define CLOCK_BUSCLOCK (DEFAULT_SYSTEM_CLOCK / 2)
60 
66 #define PIT_NUMOF (2U)
67 #define PIT_CONFIG { \
68  { \
69  .prescaler_ch = 0, \
70  .count_ch = 1, \
71  }, \
72  { \
73  .prescaler_ch = 2, \
74  .count_ch = 3, \
75  }, \
76  }
77 #define LPTMR_NUMOF (1U)
78 #define LPTMR_CONFIG { \
79  { \
80  .dev = LPTMR0, \
81  .clk_gate = (uint32_t volatile *)BITBAND_REGADDR(SIM->SCGC5, SIM_SCGC5_LPTIMER_SHIFT), \
82  .index = 0, \
83  } \
84  }
85 #define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
86 
87 #define PIT_BASECLOCK (CLOCK_BUSCLOCK)
88 #define PIT_CLOCKGATE (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_PIT_SHIFT))
89 #define PIT_ISR_0 isr_pit1
90 #define PIT_ISR_1 isr_pit3
91 #define LPTMR_ISR_0 isr_lptmr0
92 
99 #define UART_NUMOF (2U)
100 #define UART_0_EN 1
101 #define UART_1_EN 1
102 #define UART_2_EN 0
103 #define UART_3_EN 0
104 #define UART_4_EN 0
105 #define UART_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
106 
107 /* UART 0 device configuration */
108 #define UART_0_DEV UART1
109 #define UART_0_CLKEN() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_UART1_SHIFT) = 1)
110 #define UART_0_CLKDIS() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_UART1_SHIFT) = 0)
111 #define UART_0_CLK (SystemSysClock)
112 #define UART_0_IRQ_CHAN UART1_RX_TX_IRQn
113 #define UART_0_ISR isr_uart1_status
114 /* UART 0 pin configuration */
115 #define UART_0_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
116 #define UART_0_PORT PORTC
117 #define UART_0_TX_PIN 4
118 #define UART_0_RX_PIN 3
119 /* Function number in pin multiplex, see K60 Sub-Family Reference Manual,
120  * section 10.3.1 K60 Signal Multiplexing and Pin Assignments */
121 #define UART_0_AF 3
122 #define UART_0_TX_PCR_MUX 3
123 #define UART_0_RX_PCR_MUX 3
124 
125 /* UART 1 device configuration */
126 #define UART_1_DEV UART0
127 #define UART_1_CLKEN() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_UART0_SHIFT) = 1)
128 #define UART_1_CLKDIS() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_UART0_SHIFT) = 0)
129 #define UART_1_CLK (SystemSysClock)
130 #define UART_1_IRQ_CHAN UART0_RX_TX_IRQn
131 #define UART_1_ISR isr_uart0_status
132 /* UART 1 pin configuration */
133 #define UART_1_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTA_SHIFT) = 1)
134 #define UART_1_PORT PORTA
135 #define UART_1_TX_PIN 14
136 #define UART_1_RX_PIN 15
137 /* Function number in pin multiplex, see K60 Sub-Family Reference Manual,
138  * section 10.3.1 K60 Signal Multiplexing and Pin Assignments */
139 #define UART_1_AF 3
140 #define UART_1_TX_PCR_MUX 3
141 #define UART_1_RX_PCR_MUX 3
142 
149 static const adc_conf_t adc_config[] = {
150  /* dev, pin, channel */
151  [ 0] = { ADC1, GPIO_UNDEF, 26 }, /* internal: temperature sensor */
152  [ 1] = { ADC1, GPIO_UNDEF, 27 }, /* internal: band gap */
153  [ 2] = { ADC1, GPIO_UNDEF, 29 }, /* internal: V_REFSH */
154  [ 3] = { ADC1, GPIO_UNDEF, 30 }, /* internal: V_REFSL */
155  [ 4] = { ADC1, GPIO_UNDEF, 23 }, /* internal: DAC0 module output level */
156  [ 5] = { ADC1, GPIO_UNDEF, 18 }, /* internal: VREF module output level */
157  [ 6] = { ADC1, GPIO_UNDEF, 0 }, /* on board connection to Mulle Vbat/2 on PGA1_DP pin */
158  [ 7] = { ADC1, GPIO_UNDEF, 19 }, /* on board connection to Mulle Vchr/2 on PGA1_DM pin */
159  [ 8] = { ADC0, GPIO_UNDEF, 0 }, /* expansion port PGA0_DP pin */
160  [ 9] = { ADC0, GPIO_UNDEF, 19 }, /* expansion port PGA0_DM pin */
161  [10] = { ADC1, GPIO_PIN(PORT_A, 17), 17 }, /* expansion port PTA17 */
162  [11] = { ADC1, GPIO_PIN(PORT_B, 0), 8 }, /* expansion port PTB0 */
163  [12] = { ADC0, GPIO_PIN(PORT_C, 0), 14 }, /* expansion port PTC0 */
164  [13] = { ADC1, GPIO_PIN(PORT_C, 8), 4 }, /* expansion port PTC8 */
165  [14] = { ADC1, GPIO_PIN(PORT_C, 9), 5 }, /* expansion port PTC9 */
166  [15] = { ADC1, GPIO_PIN(PORT_C, 10), 6 }, /* expansion port PTC10 */
167  [16] = { ADC1, GPIO_PIN(PORT_C, 11), 7 }, /* expansion port PTC11 */
168 };
169 
170 #define ADC_NUMOF (sizeof(adc_config) / sizeof(adc_config[0]))
171 
178 #define DAC_CONFIG { \
179  { DAC0, (uint32_t volatile *)BITBAND_REGADDR(SIM->SCGC2, SIM_SCGC2_DAC0_SHIFT) }, \
180  }
181 #define DAC_NUMOF 1
182 
189 static const pwm_conf_t pwm_config[] = {
190  {
191  .ftm = FTM0,
192  .chan = {
193  { .pin = GPIO_PIN(PORT_C, 1), .af = 4, .ftm_chan = 0 },
194  { .pin = GPIO_PIN(PORT_C, 2), .af = 4, .ftm_chan = 1 },
195  { .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 },
196  { .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 }
197  },
198  .chan_numof = 2,
199  .ftm_num = 0
200  },
201  {
202  .ftm = FTM1,
203  .chan = {
204  { .pin = GPIO_PIN(PORT_A, 12), .af = 3, .ftm_chan = 0 },
205  { .pin = GPIO_PIN(PORT_A, 13), .af = 3, .ftm_chan = 1 },
206  { .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 },
207  { .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 }
208  },
209  .chan_numof = 2,
210  .ftm_num = 1
211  }
212 };
213 
214 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
215 
227 static const uint32_t spi_clk_config[] = {
228  (
229  SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | /* -> 93728Hz */
230  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
231  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
232  SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
233  ),
234  (
235  SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | /* -> 374912Hz */
236  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
237  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
238  SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
239  ),
240  (
241  SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | /* -> 999765Hz */
242  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
243  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
244  SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
245  ),
246  (
247  SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | /* -> 4798873Hz */
248  SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
249  SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
250  SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
251  ),
252  (
253  SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 7998122Hz */
254  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
255  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
256  SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
257  )
258 };
259 
260 static const spi_conf_t spi_config[] = {
261  {
262  .dev = SPI0,
263  .pin_miso = GPIO_PIN(PORT_D, 3),
264  .pin_mosi = GPIO_PIN(PORT_D, 2),
265  .pin_clk = GPIO_PIN(PORT_D, 1),
266  .pin_cs = {
267  GPIO_PIN(PORT_D, 0),
268  GPIO_UNDEF,
269  GPIO_UNDEF,
270  GPIO_UNDEF,
271  GPIO_UNDEF
272  },
273  .pcr = GPIO_AF_2,
274  .simmask = SIM_SCGC6_SPI0_MASK
275  },
276  {
277  .dev = SPI1,
278  .pin_miso = GPIO_PIN(PORT_E, 3),
279  .pin_mosi = GPIO_PIN(PORT_E, 1),
280  .pin_clk = GPIO_PIN(PORT_E, 2),
281  .pin_cs = {
282  GPIO_PIN(PORT_E, 4),
283  GPIO_UNDEF,
284  GPIO_UNDEF,
285  GPIO_UNDEF,
286  GPIO_UNDEF
287  },
288  .pcr = GPIO_AF_2,
289  .simmask = SIM_SCGC6_SPI1_MASK
290  }
291 };
292 
293 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
294 
300 /* Low (10 kHz): MUL = 4, SCL divider = 2560, total: 10240 */
301 #define KINETIS_I2C_F_ICR_LOW (0x3D)
302 #define KINETIS_I2C_F_MULT_LOW (2)
303 /* Normal (100 kHz): MUL = 2, SCL divider = 240, total: 480 */
304 #define KINETIS_I2C_F_ICR_NORMAL (0x1F)
305 #define KINETIS_I2C_F_MULT_NORMAL (1)
306 /* Fast (400 kHz): MUL = 1, SCL divider = 128, total: 128 */
307 #define KINETIS_I2C_F_ICR_FAST (0x17)
308 #define KINETIS_I2C_F_MULT_FAST (0)
309 /* Fast plus (1000 kHz): MUL = 1, SCL divider = 48, total: 48 */
310 #define KINETIS_I2C_F_ICR_FAST_PLUS (0x10)
311 #define KINETIS_I2C_F_MULT_FAST_PLUS (0)
312 
318 #define I2C_NUMOF (1U)
319 #define I2C_CLK SystemBusClock
320 #define I2C_0_EN 1
321 #define I2C_1_EN 0
322 #define I2C_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
323 
324 /* I2C 0 device configuration */
325 #define I2C_0_DEV I2C0
326 #define I2C_0_CLKEN() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_I2C0_SHIFT) = 1)
327 #define I2C_0_CLKDIS() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_I2C0_SHIFT) = 0)
328 #define I2C_0_IRQ I2C0_IRQn
329 #define I2C_0_IRQ_HANDLER isr_i2c0
330 /* I2C 0 pin configuration */
331 #define I2C_0_PORT PORTB
332 #define I2C_0_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
333 #define I2C_0_PIN_AF 2
334 #define I2C_0_SDA_PIN 1
335 #define I2C_0_SCL_PIN 2
336 #define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
337 
343 #define GPIO_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
344 
351 /* RIOT RTC implementation uses RTT for underlying timekeeper */
352 #define RTC_NUMOF (1U)
353 
359 #define RTT_NUMOF (1U)
360 #define RTT_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
361 #define RTT_IRQ RTC_IRQn
362 #define RTT_ISR isr_rtc_alarm
363 #define RTT_DEV RTC
364 #define RTT_UNLOCK() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_RTC_SHIFT) = 1)
365 #define RTT_MAX_VALUE (0xffffffff)
366 #define RTT_FREQUENCY (1) /* in Hz */
367 
371 /* The crystal on the Mulle is designed for 12.5 pF load capacitance. According
372  * to the data sheet, the K60 will have a 5 pF parasitic capacitance on the
373  * XTAL32/EXTAL32 connection. The board traces might give some minor parasitic
374  * capacitance as well. */
375 /* enable 6pF load capacitance, might need adjusting.. */
376 #define RTT_LOAD_CAP_BITS (RTC_CR_SC4P_MASK | RTC_CR_SC2P_MASK | RTC_CR_SC1P_MASK)
377 
384 #define HWRNG_CLKEN() (BITBAND_REG32(SIM->SCGC3, SIM_SCGC3_RNGA_SHIFT) = 1)
385 #define HWRNG_CLKDIS() (BITBAND_REG32(SIM->SCGC3, SIM_SCGC3_RNGA_SHIFT) = 0)
386 
388 #ifdef __cplusplus
389 }
390 #endif
391 
392 #endif /* MULLE_PERIPH_CONF_H */
393 
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
PWM configuration structure.
use alternate function 2
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
CPU specific ADC configuration.
cc2538_ssi_t * dev
SSI device.