boards/mulle/include/periph_conf.h
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1 /*
2  * Copyright (C) 2015 Eistec AB
3  * 2016 Freie Universit├Ąt Berlin
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser General
6  * Public License v2.1. See the file LICENSE in the top level directory for more
7  * details.
8  */
9 
10 
22 #ifndef MULLE_PERIPH_CONF_H
23 #define MULLE_PERIPH_CONF_H
24 
25 #include "periph_cpu.h"
26 
27 #ifdef __cplusplus
28 extern "C"
29 {
30 #endif
31 
36 #define KINETIS_CPU_USE_MCG 1
37 
38 #define KINETIS_MCG_USE_ERC 1
39 #define KINETIS_MCG_USE_PLL 0
40 #define KINETIS_MCG_DCO_RANGE (96000000U)
41 #define KINETIS_MCG_ERC_OSCILLATOR 0
42 #define KINETIS_MCG_ERC_FRDIV 0
43 #define KINETIS_MCG_ERC_RANGE 0
44 #define KINETIS_MCG_ERC_FREQ (32768U)
45 
47 #define CPU_XTAL_CLK_HZ 8000000u
48 
49 #define CPU_XTAL32k_CLK_HZ 32768u
50 
51 #define CPU_INT_SLOW_CLK_HZ 32768u
52 
53 #define CPU_INT_FAST_CLK_HZ 4000000u
54 
55 #define DEFAULT_SYSTEM_CLOCK (CPU_XTAL32k_CLK_HZ * 2929u)
56 
57 /* bus clock for the peripherals */
58 #define CLOCK_CORECLOCK (DEFAULT_SYSTEM_CLOCK)
59 #define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 2)
60 
66 #define PIT_NUMOF (2U)
67 #define PIT_CONFIG { \
68  { \
69  .prescaler_ch = 0, \
70  .count_ch = 1, \
71  }, \
72  { \
73  .prescaler_ch = 2, \
74  .count_ch = 3, \
75  }, \
76  }
77 #define LPTMR_NUMOF (1U)
78 #define LPTMR_CONFIG { \
79  { \
80  .dev = LPTMR0, \
81  .clk_gate = (uint32_t volatile *)BITBAND_REGADDR(SIM->SCGC5, SIM_SCGC5_LPTIMER_SHIFT), \
82  .index = 0, \
83  } \
84  }
85 #define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
86 
87 #define PIT_BASECLOCK (CLOCK_BUSCLOCK)
88 #define PIT_CLOCKGATE (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_PIT_SHIFT))
89 #define PIT_ISR_0 isr_pit1
90 #define PIT_ISR_1 isr_pit3
91 #define LPTMR_ISR_0 isr_lptmr0
92 
99 static const uart_conf_t uart_config[] = {
100  {
101  .dev = UART0,
102  .clken = (volatile uint32_t*)(BITBAND_REGADDR(SIM->SCGC4, SIM_SCGC4_UART0_SHIFT)),
103  .freq = CLOCK_CORECLOCK,
104  .pin_rx = GPIO_PIN(PORT_A, 14),
105  .pin_tx = GPIO_PIN(PORT_A, 15),
106  .pcr_rx = PORT_PCR_MUX(3),
107  .pcr_tx = PORT_PCR_MUX(3),
108  .irqn = UART0_RX_TX_IRQn,
109  },
110  {
111  .dev = UART1,
112  .clken = (volatile uint32_t*)(BITBAND_REGADDR(SIM->SCGC4, SIM_SCGC4_UART1_SHIFT)),
113  .freq = CLOCK_CORECLOCK,
114  .pin_rx = GPIO_PIN(PORT_C, 3),
115  .pin_tx = GPIO_PIN(PORT_C, 4),
116  .pcr_rx = PORT_PCR_MUX(3),
117  .pcr_tx = PORT_PCR_MUX(3),
118  .irqn = UART1_RX_TX_IRQn,
119  },
120 };
121 
122 #define UART_0_ISR (isr_uart0_rx_tx)
123 #define UART_1_ISR (isr_uart1_rx_tx)
124 
125 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
126 
132 static const adc_conf_t adc_config[] = {
133  /* dev, pin, channel */
134  [ 0] = { ADC1, GPIO_UNDEF, 26 }, /* internal: temperature sensor */
135  [ 1] = { ADC1, GPIO_UNDEF, 27 }, /* internal: band gap */
136  [ 2] = { ADC1, GPIO_UNDEF, 29 }, /* internal: V_REFSH */
137  [ 3] = { ADC1, GPIO_UNDEF, 30 }, /* internal: V_REFSL */
138  [ 4] = { ADC1, GPIO_UNDEF, 23 }, /* internal: DAC0 module output level */
139  [ 5] = { ADC1, GPIO_UNDEF, 18 }, /* internal: VREF module output level */
140  [ 6] = { ADC1, GPIO_UNDEF, 0 }, /* on board connection to Mulle Vbat/2 on PGA1_DP pin */
141  [ 7] = { ADC1, GPIO_UNDEF, 19 }, /* on board connection to Mulle Vchr/2 on PGA1_DM pin */
142  [ 8] = { ADC0, GPIO_UNDEF, 0 }, /* expansion port PGA0_DP pin */
143  [ 9] = { ADC0, GPIO_UNDEF, 19 }, /* expansion port PGA0_DM pin */
144  [10] = { ADC1, GPIO_PIN(PORT_A, 17), 17 }, /* expansion port PTA17 */
145  [11] = { ADC1, GPIO_PIN(PORT_B, 0), 8 }, /* expansion port PTB0 */
146  [12] = { ADC0, GPIO_PIN(PORT_C, 0), 14 }, /* expansion port PTC0 */
147  [13] = { ADC1, GPIO_PIN(PORT_C, 8), 4 }, /* expansion port PTC8 */
148  [14] = { ADC1, GPIO_PIN(PORT_C, 9), 5 }, /* expansion port PTC9 */
149  [15] = { ADC1, GPIO_PIN(PORT_C, 10), 6 }, /* expansion port PTC10 */
150  [16] = { ADC1, GPIO_PIN(PORT_C, 11), 7 }, /* expansion port PTC11 */
151 };
152 
153 #define ADC_NUMOF (sizeof(adc_config) / sizeof(adc_config[0]))
154 
161 #define DAC_CONFIG { \
162  { DAC0, (uint32_t volatile *)BITBAND_REGADDR(SIM->SCGC2, SIM_SCGC2_DAC0_SHIFT) }, \
163  }
164 #define DAC_NUMOF 1
165 
172 static const pwm_conf_t pwm_config[] = {
173  {
174  .ftm = FTM0,
175  .chan = {
176  { .pin = GPIO_PIN(PORT_C, 1), .af = 4, .ftm_chan = 0 },
177  { .pin = GPIO_PIN(PORT_C, 2), .af = 4, .ftm_chan = 1 },
178  { .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 },
179  { .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 }
180  },
181  .chan_numof = 2,
182  .ftm_num = 0
183  },
184  {
185  .ftm = FTM1,
186  .chan = {
187  { .pin = GPIO_PIN(PORT_A, 12), .af = 3, .ftm_chan = 0 },
188  { .pin = GPIO_PIN(PORT_A, 13), .af = 3, .ftm_chan = 1 },
189  { .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 },
190  { .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 }
191  },
192  .chan_numof = 2,
193  .ftm_num = 1
194  }
195 };
196 
197 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
198 
210 static const uint32_t spi_clk_config[] = {
211  (
212  SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | /* -> 93728Hz */
213  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
214  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
215  SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
216  ),
217  (
218  SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | /* -> 374912Hz */
219  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
220  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
221  SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
222  ),
223  (
224  SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | /* -> 999765Hz */
225  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
226  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
227  SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
228  ),
229  (
230  SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | /* -> 4798873Hz */
231  SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
232  SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
233  SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
234  ),
235  (
236  SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 7998122Hz */
237  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
238  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
239  SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
240  )
241 };
242 
243 static const spi_conf_t spi_config[] = {
244  {
245  .dev = SPI0,
246  .pin_miso = GPIO_PIN(PORT_D, 3),
247  .pin_mosi = GPIO_PIN(PORT_D, 2),
248  .pin_clk = GPIO_PIN(PORT_D, 1),
249  .pin_cs = {
250  GPIO_PIN(PORT_D, 0),
251  GPIO_PIN(PORT_D, 4),
252  GPIO_PIN(PORT_D, 5),
253  GPIO_PIN(PORT_D, 6),
254  GPIO_UNDEF
255  },
256  .pcr = GPIO_AF_2,
257  .simmask = SIM_SCGC6_SPI0_MASK
258  },
259  {
260  .dev = SPI1,
261  .pin_miso = GPIO_PIN(PORT_E, 3),
262  .pin_mosi = GPIO_PIN(PORT_E, 1),
263  .pin_clk = GPIO_PIN(PORT_E, 2),
264  .pin_cs = {
265  GPIO_PIN(PORT_E, 4),
266  GPIO_UNDEF,
267  GPIO_UNDEF,
268  GPIO_UNDEF,
269  GPIO_UNDEF
270  },
271  .pcr = GPIO_AF_2,
272  .simmask = SIM_SCGC6_SPI1_MASK
273  }
274 };
275 
276 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
277 
285 #define I2C_NUMOF (1U)
286 #define I2C_CLK CLOCK_BUSCLOCK
287 #define I2C_0_EN 1
288 #define I2C_1_EN 0
289 #define I2C_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
290 
291 /* I2C 0 device configuration */
292 #define I2C_0_DEV I2C0
293 #define I2C_0_CLKEN() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_I2C0_SHIFT) = 1)
294 #define I2C_0_CLKDIS() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_I2C0_SHIFT) = 0)
295 #define I2C_0_IRQ I2C0_IRQn
296 #define I2C_0_IRQ_HANDLER isr_i2c0
297 /* I2C 0 pin configuration */
298 #define I2C_0_PORT PORTB
299 #define I2C_0_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
300 #define I2C_0_PIN_AF 2
301 #define I2C_0_SDA_PIN 1
302 #define I2C_0_SCL_PIN 2
303 #define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
304 
310 /* Low (10 kHz): MUL = 4, SCL divider = 2560, total: 10240 */
311 #define KINETIS_I2C_F_ICR_LOW (0x3D)
312 #define KINETIS_I2C_F_MULT_LOW (2)
313 /* Normal (100 kHz): MUL = 2, SCL divider = 240, total: 480 */
314 #define KINETIS_I2C_F_ICR_NORMAL (0x1F)
315 #define KINETIS_I2C_F_MULT_NORMAL (1)
316 /* Fast (400 kHz): MUL = 1, SCL divider = 128, total: 128 */
317 #define KINETIS_I2C_F_ICR_FAST (0x17)
318 #define KINETIS_I2C_F_MULT_FAST (0)
319 /* Fast plus (1000 kHz): MUL = 1, SCL divider = 48, total: 48 */
320 #define KINETIS_I2C_F_ICR_FAST_PLUS (0x10)
321 #define KINETIS_I2C_F_MULT_FAST_PLUS (0)
322 
328 #define GPIO_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
329 
336 /* RIOT RTC implementation uses RTT for underlying timekeeper */
337 #define RTC_NUMOF (1U)
338 
344 #define RTT_NUMOF (1U)
345 #define RTT_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
346 #define RTT_IRQ RTC_IRQn
347 #define RTT_ISR isr_rtc_alarm
348 #define RTT_DEV RTC
349 #define RTT_UNLOCK() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_RTC_SHIFT) = 1)
350 #define RTT_MAX_VALUE (0xffffffff)
351 #define RTT_FREQUENCY (1) /* in Hz */
352 
356 /* The crystal on the Mulle is designed for 12.5 pF load capacitance. According
357  * to the data sheet, the K60 will have a 5 pF parasitic capacitance on the
358  * XTAL32/EXTAL32 connection. The board traces might give some minor parasitic
359  * capacitance as well. */
360 /* enable 6pF load capacitance, might need adjusting.. */
361 #define RTT_LOAD_CAP_BITS (RTC_CR_SC4P_MASK | RTC_CR_SC2P_MASK | RTC_CR_SC1P_MASK)
362 
369 #define HWRNG_CLKEN() (BITBAND_REG32(SIM->SCGC3, SIM_SCGC3_RNGA_SHIFT) = 1)
370 #define HWRNG_CLKDIS() (BITBAND_REG32(SIM->SCGC3, SIM_SCGC3_RNGA_SHIFT) = 0)
371 
373 #ifdef __cplusplus
374 }
375 #endif
376 
377 #endif /* MULLE_PERIPH_CONF_H */
378 
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
cc2538_uart_t *const UART0
UART0 Instance.
PWM configuration structure.
use alternate function 2
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
CPU specific ADC configuration.
cc2538_uart_t *const UART1
UART1 Instance.
cc2538_ssi_t * dev
SSI device.