boards/mulle/include/periph_conf.h
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1 /*
2  * Copyright (C) 2015 Eistec AB
3  * 2016 Freie Universit├Ąt Berlin
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser General
6  * Public License v2.1. See the file LICENSE in the top level directory for more
7  * details.
8  */
9 
10 
22 #ifndef PERIPH_CONF_H
23 #define PERIPH_CONF_H
24 
25 #include "periph_cpu.h"
26 
27 #ifdef __cplusplus
28 extern "C"
29 {
30 #endif
31 
36 static const clock_config_t clock_config = {
37  /*
38  * This configuration results in the system running from the FLL output with
39  * the following clock frequencies:
40  * Core: 48 MHz
41  * Bus: 48 MHz
42  * Flex: 24 MHz
43  * Flash: 24 MHz
44  */
45  /* The board has a 16 MHz crystal, though it is not used in this configuration */
46  /* This configuration uses the RTC crystal to provide the base clock, it
47  * should have better accuracy than the internal slow clock, and lower power
48  * consumption than using the 16 MHz crystal and the OSC0 module */
49  .clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) |
50  SIM_CLKDIV1_OUTDIV3(2) | SIM_CLKDIV1_OUTDIV4(2),
51  .default_mode = KINETIS_MCG_MODE_FEE,
52  .erc_range = KINETIS_MCG_ERC_RANGE_LOW, /* Input clock is 32768 Hz */
53  .fcrdiv = 0, /* Fast IRC divide by 1 => 4 MHz */
54  .oscsel = 1, /* Use RTC for external clock */
55  /* 16 pF capacitors yield ca 10 pF load capacitance as required by the
56  * onboard xtal, not used when OSC0 is disabled */
57  .clc = 0b0001,
58  .fll_frdiv = 0b000, /* Divide by 1 => FLL input 32768 Hz */
59  .fll_factor_fei = KINETIS_MCG_FLL_FACTOR_1464, /* FLL freq = 48 MHz */
60  .fll_factor_fee = KINETIS_MCG_FLL_FACTOR_1464, /* FLL freq = 48 MHz */
61  /* PLL is unavailable when using a 32768 Hz source clock, so the
62  * configuration below can only be used if the above config is modified to
63  * use the 16 MHz crystal instead of the RTC. */
64  .pll_prdiv = 0b00111, /* Divide by 8 */
65  .pll_vdiv = 0b01100, /* Multiply by 36 => PLL freq = 72 MHz */
66  .enable_oscillator = false, /* the RTC module provides the clock input signal */
67  .select_fast_irc = true, /* Only used for FBI mode */
68  .enable_mcgirclk = false,
69 };
70 #define CLOCK_CORECLOCK (48000000ul)
71 #define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 1)
72 
78 #define PIT_NUMOF (2U)
79 #define PIT_CONFIG { \
80  { \
81  .prescaler_ch = 0, \
82  .count_ch = 1, \
83  }, \
84  { \
85  .prescaler_ch = 2, \
86  .count_ch = 3, \
87  }, \
88  }
89 #define LPTMR_NUMOF (1U)
90 #define LPTMR_CONFIG { \
91  { \
92  .dev = LPTMR0, \
93  .irqn = LPTMR0_IRQn, \
94  } \
95  }
96 #define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
97 
98 #define PIT_BASECLOCK (CLOCK_BUSCLOCK)
99 #define PIT_ISR_0 isr_pit1
100 #define PIT_ISR_1 isr_pit3
101 #define LPTMR_ISR_0 isr_lptmr0
102 
109 static const uart_conf_t uart_config[] = {
110  {
111  .dev = UART0,
112  .freq = CLOCK_CORECLOCK,
113  .pin_rx = GPIO_PIN(PORT_A, 14),
114  .pin_tx = GPIO_PIN(PORT_A, 15),
115  .pcr_rx = PORT_PCR_MUX(3),
116  .pcr_tx = PORT_PCR_MUX(3),
117  .irqn = UART0_RX_TX_IRQn,
118  .scgc_addr = &SIM->SCGC4,
119  .scgc_bit = SIM_SCGC4_UART0_SHIFT,
120  .mode = UART_MODE_8N1
121  },
122  {
123  .dev = UART1,
124  .freq = CLOCK_CORECLOCK,
125  .pin_rx = GPIO_PIN(PORT_C, 3),
126  .pin_tx = GPIO_PIN(PORT_C, 4),
127  .pcr_rx = PORT_PCR_MUX(3),
128  .pcr_tx = PORT_PCR_MUX(3),
129  .irqn = UART1_RX_TX_IRQn,
130  .scgc_addr = &SIM->SCGC4,
131  .scgc_bit = SIM_SCGC4_UART1_SHIFT,
132  .mode = UART_MODE_8N1
133  },
134 };
135 
136 #define UART_0_ISR (isr_uart0_rx_tx)
137 #define UART_1_ISR (isr_uart1_rx_tx)
138 
139 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
140 
146 static const adc_conf_t adc_config[] = {
147  /* internal: temperature sensor */
148  [ 0] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 26 },
149  /* internal: band gap */
150  [ 1] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 27 },
151  /* internal: V_REFSH */
152  [ 2] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 29 },
153  /* internal: V_REFSL */
154  [ 3] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 30 },
155  /* internal: DAC0 module output level */
156  [ 4] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 23 },
157  /* internal: VREF module output level */
158  [ 5] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 18 },
159  /* on board connection to Mulle Vbat/2 on PGA1_DP pin */
160  [ 6] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 0 },
161  /* on board connection to Mulle Vchr/2 on PGA1_DM pin */
162  [ 7] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 19 },
163  /* expansion port PGA0_DP pin */
164  [ 8] = { .dev = ADC0, .pin = GPIO_UNDEF, .chan = 0 },
165  /* expansion port PGA0_DM pin */
166  [ 9] = { .dev = ADC0, .pin = GPIO_UNDEF, .chan = 19 },
167  /* expansion port PTA17 */
168  [10] = { .dev = ADC1, .pin = GPIO_PIN(PORT_A, 17), .chan = 17 },
169  /* expansion port PTB0 */
170  [11] = { .dev = ADC1, .pin = GPIO_PIN(PORT_B, 0), .chan = 8 },
171  /* expansion port PTC0 */
172  [12] = { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 0), .chan = 14 },
173  /* expansion port PTC8 */
174  [13] = { .dev = ADC1, .pin = GPIO_PIN(PORT_C, 8), .chan = 4 },
175  /* expansion port PTC9 */
176  [14] = { .dev = ADC1, .pin = GPIO_PIN(PORT_C, 9), .chan = 5 },
177  /* expansion port PTC10 */
178  [15] = { .dev = ADC1, .pin = GPIO_PIN(PORT_C, 10), .chan = 6 },
179  /* expansion port PTC11 */
180  [16] = { .dev = ADC1, .pin = GPIO_PIN(PORT_C, 11), .chan = 7 }
181 };
182 
183 #define ADC_NUMOF (sizeof(adc_config) / sizeof(adc_config[0]))
184 
190 static const dac_conf_t dac_config[] = {
191  {
192  .dev = DAC0,
193  .scgc_addr = &SIM->SCGC2,
194  .scgc_bit = SIM_SCGC2_DAC0_SHIFT
195  }
196 };
197 
198 #define DAC_NUMOF (sizeof(dac_config) / sizeof(dac_config[0]))
199 
205 static const pwm_conf_t pwm_config[] = {
206  {
207  .ftm = FTM0,
208  .chan = {
209  { .pin = GPIO_PIN(PORT_C, 1), .af = 4, .ftm_chan = 0 },
210  { .pin = GPIO_PIN(PORT_C, 2), .af = 4, .ftm_chan = 1 },
211  { .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 },
212  { .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 }
213  },
214  .chan_numof = 2,
215  .ftm_num = 0
216  },
217  {
218  .ftm = FTM1,
219  .chan = {
220  { .pin = GPIO_PIN(PORT_A, 12), .af = 3, .ftm_chan = 0 },
221  { .pin = GPIO_PIN(PORT_A, 13), .af = 3, .ftm_chan = 1 },
222  { .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 },
223  { .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 }
224  },
225  .chan_numof = 2,
226  .ftm_num = 1
227  }
228 };
229 
230 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
231 
243 static const uint32_t spi_clk_config[] = {
244  (
245  SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | /* -> 93728Hz */
246  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
247  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
248  SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
249  ),
250  (
251  SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | /* -> 374912Hz */
252  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
253  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
254  SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
255  ),
256  (
257  SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | /* -> 999765Hz */
258  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
259  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
260  SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
261  ),
262  (
263  SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | /* -> 4798873Hz */
264  SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
265  SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
266  SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
267  ),
268  (
269  SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 7998122Hz */
270  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
271  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
272  SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
273  )
274 };
275 
276 static const spi_conf_t spi_config[] = {
277  {
278  .dev = SPI0,
279  .pin_miso = GPIO_PIN(PORT_D, 3),
280  .pin_mosi = GPIO_PIN(PORT_D, 2),
281  .pin_clk = GPIO_PIN(PORT_D, 1),
282  .pin_cs = {
283  GPIO_PIN(PORT_D, 0),
284  GPIO_PIN(PORT_D, 4),
285  GPIO_PIN(PORT_D, 5),
286  GPIO_PIN(PORT_D, 6),
287  GPIO_UNDEF
288  },
289  .pcr = GPIO_AF_2,
290  .simmask = SIM_SCGC6_SPI0_MASK
291  },
292  {
293  .dev = SPI1,
294  .pin_miso = GPIO_PIN(PORT_E, 3),
295  .pin_mosi = GPIO_PIN(PORT_E, 1),
296  .pin_clk = GPIO_PIN(PORT_E, 2),
297  .pin_cs = {
298  GPIO_PIN(PORT_E, 4),
299  GPIO_UNDEF,
300  GPIO_UNDEF,
301  GPIO_UNDEF,
302  GPIO_UNDEF
303  },
304  .pcr = GPIO_AF_2,
305  .simmask = SIM_SCGC6_SPI1_MASK
306  }
307 };
308 
309 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
310 
318 #define I2C_NUMOF (1U)
319 #define I2C_0_EN 1
320 #define I2C_1_EN 0
321 
322 /* I2C 0 device configuration */
323 #define I2C_0_DEV I2C0
324 #define I2C_0_CLKEN() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_I2C0_SHIFT) = 1)
325 #define I2C_0_CLKDIS() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_I2C0_SHIFT) = 0)
326 #define I2C_0_IRQ I2C0_IRQn
327 #define I2C_0_IRQ_HANDLER isr_i2c0
328 /* I2C 0 pin configuration */
329 #define I2C_0_PORT PORTB
330 #define I2C_0_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
331 #define I2C_0_PIN_AF 2
332 #define I2C_0_SDA_PIN 1
333 #define I2C_0_SCL_PIN 2
334 #define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
335 
341 /* Low (10 kHz): MUL = 2, SCL divider = 2560, total: 5120 */
342 #define KINETIS_I2C_F_ICR_LOW (0x3D)
343 #define KINETIS_I2C_F_MULT_LOW (1)
344 /* Normal (100 kHz): MUL = 2, SCL divider = 240, total: 480 */
345 #define KINETIS_I2C_F_ICR_NORMAL (0x1F)
346 #define KINETIS_I2C_F_MULT_NORMAL (1)
347 /* Fast (400 kHz): MUL = 1, SCL divider = 128, total: 128 */
348 #define KINETIS_I2C_F_ICR_FAST (0x17)
349 #define KINETIS_I2C_F_MULT_FAST (0)
350 /* Fast plus (1000 kHz): MUL = 1, SCL divider = 48, total: 48 */
351 #define KINETIS_I2C_F_ICR_FAST_PLUS (0x10)
352 #define KINETIS_I2C_F_MULT_FAST_PLUS (0)
353 
359 /* RIOT RTC implementation uses RTT for underlying timekeeper */
360 #define RTC_NUMOF (1U)
361 
367 #define RTT_NUMOF (1U)
368 #define RTT_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
369 #define RTT_IRQ RTC_IRQn
370 #define RTT_ISR isr_rtc_alarm
371 #define RTT_DEV RTC
372 #define RTT_UNLOCK() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_RTC_SHIFT) = 1)
373 #define RTT_MAX_VALUE (0xffffffff)
374 #define RTT_FREQUENCY (1) /* in Hz */
375 
379 /* The crystal on the Mulle is designed for 12.5 pF load capacitance. According
380  * to the data sheet, the K60 will have a 5 pF parasitic capacitance on the
381  * XTAL32/EXTAL32 connection. The board traces might give some minor parasitic
382  * capacitance as well. */
383 /* Use the equation
384  * CL = (C1 * C2) / (C1 + C2) + Cstray
385  * with C1 == C2:
386  * C1 = 2 * (CL - Cstray)
387  */
388 /* enable 14pF load capacitor which will yield a crystal load capacitance of 12 pF */
389 #define RTC_LOAD_CAP_BITS (RTC_CR_SC8P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC2P_MASK)
390 
398 #define HWRNG_CLKEN() (BITBAND_REG32(SIM->SCGC3, SIM_SCGC3_RNGA_SHIFT) = 1)
399 #define HWRNG_CLKDIS() (BITBAND_REG32(SIM->SCGC3, SIM_SCGC3_RNGA_SHIFT) = 0)
400 
402 #ifdef __cplusplus
403 }
404 #endif
405 
406 #endif /* PERIPH_CONF_H */
407 
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
#define CLOCK_CORECLOCK
Core clock frequency, used by the ARM core and certain hardware modules in Kinetis CPUs...
Definition: mcg.h:137
cc2538_uart_t *const UART0
UART0 Instance.
PWM configuration structure.
uint32_t clkdiv1
Clock divider bitfield setting, see reference manual for SIM_CLKDIV1.
ADC_Type * dev
ADC device.
use alternate function 2
#define UART_MODE_8N1
8 data bits, no parity, 1 stop bit
Clock configuration for Kinetis CPUs.
UART device configuration.
DAC line configuration data.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI module configuration options.
CPU specific ADC configuration.
cc2538_uart_t *const UART1
UART1 Instance.
cc2538_ssi_t * dev
SSI device.