boards/mulle/include/periph_conf.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2015 Eistec AB
3  * 2016 Freie Universit├Ąt Berlin
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser General
6  * Public License v2.1. See the file LICENSE in the top level directory for more
7  * details.
8  */
9 
10 
22 #ifndef PERIPH_CONF_H
23 #define PERIPH_CONF_H
24 
25 #include "periph_cpu.h"
26 
27 #ifdef __cplusplus
28 extern "C"
29 {
30 #endif
31 
36 /* The crystal on the Mulle is designed for 12.5 pF load capacitance. According
37  * to the data sheet, the K60 will have a 5 pF parasitic capacitance on the
38  * XTAL32/EXTAL32 connection. The board traces might give some minor parasitic
39  * capacitance as well. */
40 /* Use the equation
41  * CL = (C1 * C2) / (C1 + C2) + Cstray
42  * with C1 == C2:
43  * C1 = 2 * (CL - Cstray)
44  */
45 /* enable 14pF load capacitor which will yield a crystal load capacitance of 12 pF */
46 #define RTC_LOAD_CAP_BITS (RTC_CR_SC8P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC2P_MASK)
47 
48 static const clock_config_t clock_config = {
49  /*
50  * This configuration results in the system running from the FLL output with
51  * the following clock frequencies:
52  * Core: 48 MHz
53  * Bus: 48 MHz
54  * Flex: 24 MHz
55  * Flash: 24 MHz
56  */
57  /* The board has a 16 MHz crystal, though it is not used in this configuration */
58  /* This configuration uses the RTC crystal to provide the base clock, it
59  * should have better accuracy than the internal slow clock, and lower power
60  * consumption than using the 16 MHz crystal and the OSC0 module */
61  .clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) |
62  SIM_CLKDIV1_OUTDIV3(1) | SIM_CLKDIV1_OUTDIV4(1),
63  .rtc_clc = RTC_LOAD_CAP_BITS,
64  .osc32ksel = SIM_SOPT1_OSC32KSEL(2),
65  .clock_flags =
66  /* no OSC0_EN, the RTC module provides the clock input signal for the FLL */
69  0,
70  .default_mode = KINETIS_MCG_MODE_FEE,
71  .erc_range = KINETIS_MCG_ERC_RANGE_LOW, /* Input clock is 32768 Hz */
72  /* 16 pF capacitors yield ca 10 pF load capacitance as required by the
73  * onboard xtal, not used when OSC0 is disabled */
74  .osc_clc = OSC_CR_SC16P_MASK,
75  .oscsel = MCG_C7_OSCSEL(1), /* Use RTC for external clock */
76  .fcrdiv = MCG_SC_FCRDIV(0), /* Fast IRC divide by 1 => 4 MHz */
77  .fll_frdiv = MCG_C1_FRDIV(0b000), /* Divide by 1 => FLL input 32768 Hz */
78  .fll_factor_fei = KINETIS_MCG_FLL_FACTOR_1464, /* FLL freq = 48 MHz */
79  .fll_factor_fee = KINETIS_MCG_FLL_FACTOR_1464, /* FLL freq = 48 MHz */
80  /* PLL is unavailable when using a 32768 Hz source clock, so the
81  * configuration below can only be used if the above config is modified to
82  * use the 16 MHz crystal instead of the RTC. */
83  .pll_prdiv = MCG_C5_PRDIV0(0b00111), /* Divide by 8 */
84  .pll_vdiv = MCG_C6_VDIV0(0b01100), /* Multiply by 36 => PLL freq = 72 MHz */
85 };
86 #define CLOCK_CORECLOCK (48000000ul)
87 #define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 1)
88 
94 #define PIT_NUMOF (2U)
95 #define PIT_CONFIG { \
96  { \
97  .prescaler_ch = 0, \
98  .count_ch = 1, \
99  }, \
100  { \
101  .prescaler_ch = 2, \
102  .count_ch = 3, \
103  }, \
104  }
105 #define LPTMR_NUMOF (1U)
106 #define LPTMR_CONFIG { \
107  { \
108  .dev = LPTMR0, \
109  .irqn = LPTMR0_IRQn, \
110  } \
111  }
112 #define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
113 
114 #define PIT_BASECLOCK (CLOCK_BUSCLOCK)
115 #define PIT_ISR_0 isr_pit1
116 #define PIT_ISR_1 isr_pit3
117 #define LPTMR_ISR_0 isr_lptmr0
118 
124 static const uart_conf_t uart_config[] = {
125  {
126  .dev = UART0,
127  .freq = CLOCK_CORECLOCK,
128  .pin_rx = GPIO_PIN(PORT_A, 14),
129  .pin_tx = GPIO_PIN(PORT_A, 15),
130  .pcr_rx = PORT_PCR_MUX(3),
131  .pcr_tx = PORT_PCR_MUX(3),
132  .irqn = UART0_RX_TX_IRQn,
133  .scgc_addr = &SIM->SCGC4,
134  .scgc_bit = SIM_SCGC4_UART0_SHIFT,
135  .mode = UART_MODE_8N1,
136  .type = KINETIS_UART,
137  },
138  {
139  .dev = UART1,
140  .freq = CLOCK_CORECLOCK,
141  .pin_rx = GPIO_PIN(PORT_C, 3),
142  .pin_tx = GPIO_PIN(PORT_C, 4),
143  .pcr_rx = PORT_PCR_MUX(3),
144  .pcr_tx = PORT_PCR_MUX(3),
145  .irqn = UART1_RX_TX_IRQn,
146  .scgc_addr = &SIM->SCGC4,
147  .scgc_bit = SIM_SCGC4_UART1_SHIFT,
148  .mode = UART_MODE_8N1,
149  .type = KINETIS_UART,
150  },
151 };
152 
153 #define UART_0_ISR (isr_uart0_rx_tx)
154 #define UART_1_ISR (isr_uart1_rx_tx)
155 
156 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
157 
163 static const adc_conf_t adc_config[] = {
164  /* internal: temperature sensor */
165  [ 0] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 26 },
166  /* internal: band gap */
167  [ 1] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 27 },
168  /* internal: V_REFSH */
169  [ 2] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 29 },
170  /* internal: V_REFSL */
171  [ 3] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 30 },
172  /* internal: DAC0 module output level */
173  [ 4] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 23 },
174  /* internal: VREF module output level */
175  [ 5] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 18 },
176  /* on board connection to Mulle Vbat/2 on PGA1_DP pin */
177  [ 6] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 0 },
178  /* on board connection to Mulle Vchr/2 on PGA1_DM pin */
179  [ 7] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 19 },
180  /* expansion port PGA0_DP pin */
181  [ 8] = { .dev = ADC0, .pin = GPIO_UNDEF, .chan = 0 },
182  /* expansion port PGA0_DM pin */
183  [ 9] = { .dev = ADC0, .pin = GPIO_UNDEF, .chan = 19 },
184  /* expansion port PTA17 */
185  [10] = { .dev = ADC1, .pin = GPIO_PIN(PORT_A, 17), .chan = 17 },
186  /* expansion port PTB0 */
187  [11] = { .dev = ADC1, .pin = GPIO_PIN(PORT_B, 0), .chan = 8 },
188  /* expansion port PTC0 */
189  [12] = { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 0), .chan = 14 },
190  /* expansion port PTC8 */
191  [13] = { .dev = ADC1, .pin = GPIO_PIN(PORT_C, 8), .chan = 4 },
192  /* expansion port PTC9 */
193  [14] = { .dev = ADC1, .pin = GPIO_PIN(PORT_C, 9), .chan = 5 },
194  /* expansion port PTC10 */
195  [15] = { .dev = ADC1, .pin = GPIO_PIN(PORT_C, 10), .chan = 6 },
196  /* expansion port PTC11 */
197  [16] = { .dev = ADC1, .pin = GPIO_PIN(PORT_C, 11), .chan = 7 }
198 };
199 
200 #define ADC_NUMOF (sizeof(adc_config) / sizeof(adc_config[0]))
201 /*
202  * K60D ADC reference settings:
203  * 0: VREFH/VREFL external pin pair
204  * 1: VREF_OUT internal 1.2 V reference (VREF module must be enabled)
205  * 2-3: reserved
206  */
207 #define ADC_REF_SETTING 0
208 
214 static const dac_conf_t dac_config[] = {
215  {
216  .dev = DAC0,
217  .scgc_addr = &SIM->SCGC2,
218  .scgc_bit = SIM_SCGC2_DAC0_SHIFT
219  }
220 };
221 
222 #define DAC_NUMOF (sizeof(dac_config) / sizeof(dac_config[0]))
223 
229 static const pwm_conf_t pwm_config[] = {
230  {
231  .ftm = FTM0,
232  .chan = {
233  { .pin = GPIO_PIN(PORT_C, 1), .af = 4, .ftm_chan = 0 },
234  { .pin = GPIO_PIN(PORT_C, 2), .af = 4, .ftm_chan = 1 },
235  { .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 },
236  { .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 }
237  },
238  .chan_numof = 2,
239  .ftm_num = 0
240  },
241  {
242  .ftm = FTM1,
243  .chan = {
244  { .pin = GPIO_PIN(PORT_A, 12), .af = 3, .ftm_chan = 0 },
245  { .pin = GPIO_PIN(PORT_A, 13), .af = 3, .ftm_chan = 1 },
246  { .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 },
247  { .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 }
248  },
249  .chan_numof = 2,
250  .ftm_num = 1
251  }
252 };
253 
254 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
255 
267 static const uint32_t spi_clk_config[] = {
268  (
269  SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | /* -> 93728Hz */
270  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
271  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
272  SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
273  ),
274  (
275  SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | /* -> 374912Hz */
276  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
277  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
278  SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
279  ),
280  (
281  SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | /* -> 999765Hz */
282  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
283  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
284  SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
285  ),
286  (
287  SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | /* -> 4798873Hz */
288  SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
289  SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
290  SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
291  ),
292  (
293  SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 7998122Hz */
294  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
295  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
296  SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
297  )
298 };
299 
300 static const spi_conf_t spi_config[] = {
301  {
302  .dev = SPI0,
303  .pin_miso = GPIO_PIN(PORT_D, 3),
304  .pin_mosi = GPIO_PIN(PORT_D, 2),
305  .pin_clk = GPIO_PIN(PORT_D, 1),
306  .pin_cs = {
307  GPIO_PIN(PORT_D, 0),
308  GPIO_PIN(PORT_D, 4),
309  GPIO_PIN(PORT_D, 5),
310  GPIO_PIN(PORT_D, 6),
311  GPIO_UNDEF
312  },
313  .pcr = GPIO_AF_2,
314  .simmask = SIM_SCGC6_SPI0_MASK
315  },
316  {
317  .dev = SPI1,
318  .pin_miso = GPIO_PIN(PORT_E, 3),
319  .pin_mosi = GPIO_PIN(PORT_E, 1),
320  .pin_clk = GPIO_PIN(PORT_E, 2),
321  .pin_cs = {
322  GPIO_PIN(PORT_E, 4),
323  GPIO_UNDEF,
324  GPIO_UNDEF,
325  GPIO_UNDEF,
326  GPIO_UNDEF
327  },
328  .pcr = GPIO_AF_2,
329  .simmask = SIM_SCGC6_SPI1_MASK
330  }
331 };
332 
333 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
334 
340 #define I2C_NUMOF (1U)
341 #define I2C_0_EN 1
342 #define I2C_1_EN 0
343 
344 /* I2C 0 device configuration */
345 #define I2C_0_DEV I2C0
346 #define I2C_0_CLKEN() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_I2C0_SHIFT) = 1)
347 #define I2C_0_CLKDIS() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_I2C0_SHIFT) = 0)
348 #define I2C_0_IRQ I2C0_IRQn
349 #define I2C_0_IRQ_HANDLER isr_i2c0
350 /* I2C 0 pin configuration */
351 #define I2C_0_PORT PORTB
352 #define I2C_0_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
353 #define I2C_0_PIN_AF 2
354 #define I2C_0_SDA_PIN 1
355 #define I2C_0_SCL_PIN 2
356 #define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
357 
363 /* Low (10 kHz): MUL = 2, SCL divider = 2560, total: 5120 */
364 #define KINETIS_I2C_F_ICR_LOW (0x3D)
365 #define KINETIS_I2C_F_MULT_LOW (1)
366 /* Normal (100 kHz): MUL = 2, SCL divider = 240, total: 480 */
367 #define KINETIS_I2C_F_ICR_NORMAL (0x1F)
368 #define KINETIS_I2C_F_MULT_NORMAL (1)
369 /* Fast (400 kHz): MUL = 1, SCL divider = 128, total: 128 */
370 #define KINETIS_I2C_F_ICR_FAST (0x17)
371 #define KINETIS_I2C_F_MULT_FAST (0)
372 /* Fast plus (1000 kHz): MUL = 1, SCL divider = 48, total: 48 */
373 #define KINETIS_I2C_F_ICR_FAST_PLUS (0x10)
374 #define KINETIS_I2C_F_MULT_FAST_PLUS (0)
375 
381 /* RIOT RTC implementation uses RTT for underlying timekeeper */
382 #define RTC_NUMOF (1U)
383 
389 #define RTT_NUMOF (1U)
390 #define RTT_IRQ RTC_IRQn
391 #define RTT_IRQ_PRIO 10
392 #define RTT_ISR isr_rtc
393 #define RTT_DEV RTC
394 #define RTT_UNLOCK() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_RTC_SHIFT) = 1)
395 #define RTT_MAX_VALUE (0xffffffff)
396 #define RTT_FREQUENCY (1) /* in Hz */
397 
399 #ifdef __cplusplus
400 }
401 #endif
402 
403 #endif /* PERIPH_CONF_H */
404 
cc2538_uart_t * dev
pointer to the used UART device
PWM device configuration.
uint32_t clkdiv1
Clock divider bitfield setting.
pwm_conf_chan_t chan[3]
channel configuration
8 data bits, no parity, 1 stop bit
ADC_TypeDef * dev
ADC device used.
use alternate function 2
FLL Engaged External Mode.
Clock configuration for Kinetis CPUs.
for 31.25-39.0625 kHz crystal
UART device configuration.
DAC line configuration data.
SPI module configuration options.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
#define CLOCK_CORECLOCK
Core clock frequency, used by the ARM core and certain hardware modules in Kinetis CPUs...
Definition: mcg.h:137
ADC device configuration.
Use the fast internal reference clock as MCGIRCLK signal.
Kinetis UART module type.
cc2538_ssi_t * dev
SSI device.