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boards/mulle/include/periph_conf.h File Reference
#include "periph_cpu.h"
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Macros

Clock system configuration
#define KINETIS_CPU_USE_MCG   1
 
#define KINETIS_MCG_USE_ERC   1
 
#define KINETIS_MCG_USE_PLL   0
 
#define KINETIS_MCG_DCO_RANGE   (96000000U)
 
#define KINETIS_MCG_ERC_OSCILLATOR   0
 
#define KINETIS_MCG_ERC_FRDIV   0
 
#define KINETIS_MCG_ERC_RANGE   0
 
#define KINETIS_MCG_ERC_FREQ   (32768U)
 
#define CPU_XTAL_CLK_HZ   8000000u
 Value of the external crystal or oscillator clock frequency in Hz.
 
#define CPU_XTAL32k_CLK_HZ   32768u
 Value of the external 32k crystal or oscillator clock frequency in Hz.
 
#define CPU_INT_SLOW_CLK_HZ   32768u
 Value of the slow internal oscillator clock frequency in Hz.
 
#define CPU_INT_FAST_CLK_HZ   4000000u
 Value of the fast internal oscillator clock frequency in Hz.
 
#define DEFAULT_SYSTEM_CLOCK   (CPU_XTAL32k_CLK_HZ * 2929u)
 Default System clock value.
 
#define CLOCK_BUSCLOCK   (DEFAULT_SYSTEM_CLOCK / 2)
 
Timer configuration
#define PIT_NUMOF   (2U)
 
#define PIT_CONFIG
 
#define LPTMR_NUMOF   (1U)
 
#define LPTMR_CONFIG
 
#define TIMER_NUMOF   ((PIT_NUMOF) + (LPTMR_NUMOF))
 
#define PIT_BASECLOCK   (CLOCK_BUSCLOCK)
 
#define PIT_CLOCKGATE   (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_PIT_SHIFT))
 
#define PIT_ISR_0   isr_pit1
 
#define PIT_ISR_1   isr_pit3
 
#define LPTMR_ISR_0   isr_lptmr0
 
UART configuration
#define UART_NUMOF   (2U)
 
#define UART_0_EN   1
 
#define UART_1_EN   1
 
#define UART_2_EN   0
 
#define UART_3_EN   0
 
#define UART_4_EN   0
 
#define UART_IRQ_PRIO   CPU_DEFAULT_IRQ_PRIO
 
#define UART_0_DEV   UART1
 
#define UART_0_CLKEN()   (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_UART1_SHIFT) = 1)
 
#define UART_0_CLKDIS()   (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_UART1_SHIFT) = 0)
 
#define UART_0_CLK   (SystemSysClock)
 
#define UART_0_IRQ_CHAN   UART1_RX_TX_IRQn
 
#define UART_0_ISR   isr_uart1_status
 
#define UART_0_PORT_CLKEN()   (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
 
#define UART_0_PORT   PORTC
 
#define UART_0_TX_PIN   4
 
#define UART_0_RX_PIN   3
 
#define UART_0_AF   3
 
#define UART_0_TX_PCR_MUX   3
 
#define UART_0_RX_PCR_MUX   3
 
#define UART_1_DEV   UART0
 
#define UART_1_CLKEN()   (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_UART0_SHIFT) = 1)
 
#define UART_1_CLKDIS()   (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_UART0_SHIFT) = 0)
 
#define UART_1_CLK   (SystemSysClock)
 
#define UART_1_IRQ_CHAN   UART0_RX_TX_IRQn
 
#define UART_1_ISR   isr_uart0_status
 
#define UART_1_PORT_CLKEN()   (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTA_SHIFT) = 1)
 
#define UART_1_PORT   PORTA
 
#define UART_1_TX_PIN   14
 
#define UART_1_RX_PIN   15
 
#define UART_1_AF   3
 
#define UART_1_TX_PCR_MUX   3
 
#define UART_1_RX_PCR_MUX   3
 
DAC configuration
#define DAC_CONFIG
 
#define DAC_NUMOF   1
 
I2C baud rate configuration
#define KINETIS_I2C_F_ICR_LOW   (0x3D)
 
#define KINETIS_I2C_F_MULT_LOW   (2)
 
#define KINETIS_I2C_F_ICR_NORMAL   (0x1F)
 
#define KINETIS_I2C_F_MULT_NORMAL   (1)
 
#define KINETIS_I2C_F_ICR_FAST   (0x17)
 
#define KINETIS_I2C_F_MULT_FAST   (0)
 
#define KINETIS_I2C_F_ICR_FAST_PLUS   (0x10)
 
#define KINETIS_I2C_F_MULT_FAST_PLUS   (0)
 
I2C configuration
#define I2C_NUMOF   (1U)
 
#define I2C_CLK   SystemBusClock
 
#define I2C_0_EN   1
 
#define I2C_1_EN   0
 
#define I2C_IRQ_PRIO   CPU_DEFAULT_IRQ_PRIO
 
#define I2C_0_DEV   I2C0
 
#define I2C_0_CLKEN()   (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_I2C0_SHIFT) = 1)
 
#define I2C_0_CLKDIS()   (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_I2C0_SHIFT) = 0)
 
#define I2C_0_IRQ   I2C0_IRQn
 
#define I2C_0_IRQ_HANDLER   isr_i2c0
 
#define I2C_0_PORT   PORTB
 
#define I2C_0_PORT_CLKEN()   (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
 
#define I2C_0_PIN_AF   2
 
#define I2C_0_SDA_PIN   1
 
#define I2C_0_SCL_PIN   2
 
#define I2C_0_PORT_CFG   (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
 
GPIO configuration
#define GPIO_IRQ_PRIO   CPU_DEFAULT_IRQ_PRIO
 
RTC configuration
#define RTC_NUMOF   (1U)
 
RTT configuration
#define RTT_NUMOF   (1U)
 
#define RTT_IRQ_PRIO   CPU_DEFAULT_IRQ_PRIO
 
#define RTT_IRQ   RTC_IRQn
 
#define RTT_ISR   isr_rtc_alarm
 
#define RTT_DEV   RTC
 
#define RTT_UNLOCK()   (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_RTC_SHIFT) = 1)
 
#define RTT_MAX_VALUE   (0xffffffff)
 
#define RTT_FREQUENCY   (1) /* in Hz */
 
#define RTT_LOAD_CAP_BITS   (RTC_CR_SC4P_MASK | RTC_CR_SC2P_MASK | RTC_CR_SC1P_MASK)
 RTC module crystal load capacitance configuration bits.
 
Random Number Generator configuration
#define HWRNG_CLKEN()   (BITBAND_REG32(SIM->SCGC3, SIM_SCGC3_RNGA_SHIFT) = 1)
 
#define HWRNG_CLKDIS()   (BITBAND_REG32(SIM->SCGC3, SIM_SCGC3_RNGA_SHIFT) = 0)
 

ADC configuration

#define ADC_NUMOF   (sizeof(adc_config) / sizeof(adc_config[0]))
 
static const adc_conf_t adc_config []
 

PWM configuration

#define PWM_NUMOF   (sizeof(pwm_config) / sizeof(pwm_config[0]))
 
static const pwm_conf_t pwm_config []
 

SPI configuration

Clock configuration values based on the configured 47988736Hz module clock.

Auto-generated by: cpu/kinetis_common/dist/calc_spi_scalers/calc_spi_scalers.c

#define SPI_NUMOF   (sizeof(spi_config) / sizeof(spi_config[0]))
 
static const uint32_t spi_clk_config []
 
static const spi_conf_t spi_config []
 

Macro Definition Documentation

#define DAC_CONFIG
Value:
{ \
{ DAC0, (uint32_t volatile *)BITBAND_REGADDR(SIM->SCGC2, SIM_SCGC2_DAC0_SHIFT) }, \
}

Definition at line 178 of file boards/mulle/include/periph_conf.h.

#define LPTMR_CONFIG
Value:
{ \
{ \
.dev = LPTMR0, \
.clk_gate = (uint32_t volatile *)BITBAND_REGADDR(SIM->SCGC5, SIM_SCGC5_LPTIMER_SHIFT), \
.index = 0, \
} \
}

Definition at line 78 of file boards/mulle/include/periph_conf.h.

#define PIT_CONFIG
Value:
{ \
{ \
.prescaler_ch = 0, \
.count_ch = 1, \
}, \
{ \
.prescaler_ch = 2, \
.count_ch = 3, \
}, \
}

Definition at line 67 of file boards/mulle/include/periph_conf.h.

Variable Documentation

const adc_conf_t adc_config[]
static
Initial value:
= {
[ 0] = { ADC1, GPIO_UNDEF, 26 },
[ 1] = { ADC1, GPIO_UNDEF, 27 },
[ 2] = { ADC1, GPIO_UNDEF, 29 },
[ 3] = { ADC1, GPIO_UNDEF, 30 },
[ 4] = { ADC1, GPIO_UNDEF, 23 },
[ 5] = { ADC1, GPIO_UNDEF, 18 },
[ 6] = { ADC1, GPIO_UNDEF, 0 },
[ 7] = { ADC1, GPIO_UNDEF, 19 },
[ 8] = { ADC0, GPIO_UNDEF, 0 },
[ 9] = { ADC0, GPIO_UNDEF, 19 },
[10] = { ADC1, GPIO_PIN(PORT_A, 17), 17 },
[11] = { ADC1, GPIO_PIN(PORT_B, 0), 8 },
[12] = { ADC0, GPIO_PIN(PORT_C, 0), 14 },
[13] = { ADC1, GPIO_PIN(PORT_C, 8), 4 },
[14] = { ADC1, GPIO_PIN(PORT_C, 9), 5 },
[15] = { ADC1, GPIO_PIN(PORT_C, 10), 6 },
[16] = { ADC1, GPIO_PIN(PORT_C, 11), 7 },
}
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.

Definition at line 149 of file boards/mulle/include/periph_conf.h.

const pwm_conf_t pwm_config[]
static
Initial value:
= {
{
.ftm = FTM0,
.chan = {
{ .pin = GPIO_PIN(PORT_C, 1), .af = 4, .ftm_chan = 0 },
{ .pin = GPIO_PIN(PORT_C, 2), .af = 4, .ftm_chan = 1 },
{ .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 },
{ .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 }
},
.chan_numof = 2,
.ftm_num = 0
},
{
.ftm = FTM1,
.chan = {
{ .pin = GPIO_PIN(PORT_A, 12), .af = 3, .ftm_chan = 0 },
{ .pin = GPIO_PIN(PORT_A, 13), .af = 3, .ftm_chan = 1 },
{ .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 },
{ .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 }
},
.chan_numof = 2,
.ftm_num = 1
}
}
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.

Definition at line 189 of file boards/mulle/include/periph_conf.h.