boards/msbiot/include/periph_conf.h
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1 /*
2  * Copyright (C) 2014 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 /* 0: no external high speed crystal available
33  * else: actual crystal frequency [in Hz] */
34 #define CLOCK_HSE (16000000U)
35 /* 0: no external low speed crystal available,
36  * 1: external crystal available (always 32.768kHz) */
37 #define CLOCK_LSE (0)
38 /* give the target core clock (HCLK) frequency [in Hz],
39  * maximum: 168MHz */
40 #define CLOCK_CORECLOCK (168000000U)
41 /* peripheral clock setup */
42 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */
43 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
44 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */
45 #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
46 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */
47 #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
48 
54 static const timer_conf_t timer_config[] = {
55  {
56  .dev = TIM2,
57  .max = 0xffffffff,
58  .rcc_mask = RCC_APB1ENR_TIM2EN,
59  .bus = APB1,
60  .irqn = TIM2_IRQn
61  },
62  {
63  .dev = TIM5,
64  .max = 0xffffffff,
65  .rcc_mask = RCC_APB1ENR_TIM5EN,
66  .bus = APB1,
67  .irqn = TIM5_IRQn
68  }
69 };
70 
71 #define TIMER_0_ISR isr_tim2
72 #define TIMER_1_ISR isr_tim5
73 
74 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
75 
81 static const pwm_conf_t pwm_config[] = {
82  {
83  .dev = TIM11,
84  .rcc_mask = RCC_APB2ENR_TIM11EN,
85  .chan = { { .pin = GPIO_PIN(PORT_B, 9), .cc_chan = 0 },
86  { .pin = GPIO_UNDEF, .cc_chan = 0 },
87  { .pin = GPIO_UNDEF, .cc_chan = 0 },
88  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
89  .af = GPIO_AF3,
90  .bus = APB2
91  }
92 };
93 
94 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
95 
104 #define ADC_CONFIG { \
105  {GPIO_PIN(PORT_B, 0), 0, 8}, \
106  {GPIO_PIN(PORT_B, 1), 0, 9} \
107 }
108 
109 #define ADC_NUMOF (2)
110 
116 static const dac_conf_t dac_config[] = {
117  { .pin = GPIO_PIN(PORT_A, 4), .chan = 0 },
118  { .pin = GPIO_PIN(PORT_A, 5), .chan = 1 }
119 };
120 
121 #define DAC_NUMOF (sizeof(dac_config) / sizeof(dac_config[0]))
122 
128 static const uart_conf_t uart_config[] = {
129  {
130  .dev = USART2,
131  .rcc_mask = RCC_APB1ENR_USART2EN,
132  .rx_pin = GPIO_PIN(PORT_A, 3),
133  .tx_pin = GPIO_PIN(PORT_A, 2),
134  .rx_af = GPIO_AF7,
135  .tx_af = GPIO_AF7,
136  .bus = APB1,
137  .irqn = USART2_IRQn,
138 #ifdef UART_USE_DMA
139  .dma_stream = 6,
140  .dma_chan = 4
141 #endif
142  },
143  {
144  .dev = USART1,
145  .rcc_mask = RCC_APB2ENR_USART1EN,
146  .rx_pin = GPIO_PIN(PORT_A, 10),
147  .tx_pin = GPIO_PIN(PORT_A, 9),
148  .rx_af = GPIO_AF7,
149  .tx_af = GPIO_AF7,
150  .bus = APB2,
151  .irqn = USART1_IRQn,
152 #ifdef UART_USE_DMA
153  .dma_stream = 15,
154  .dma_chan = 4
155 #endif
156  },
157  {
158  .dev = USART3,
159  .rcc_mask = RCC_APB1ENR_USART3EN,
160  .rx_pin = GPIO_PIN(PORT_D, 9),
161  .tx_pin = GPIO_PIN(PORT_D, 8),
162  .rx_af = GPIO_AF7,
163  .tx_af = GPIO_AF7,
164  .bus = APB1,
165  .irqn = USART3_IRQn,
166 #ifdef UART_USE_DMA
167  .dma_stream = 3,
168  .dma_chan = 4
169 #endif
170  },
171 };
172 
173 /* assign ISR vector names */
174 #define UART_0_ISR (isr_usart2)
175 #define UART_0_DMA_ISR (isr_dma1_stream6)
176 #define UART_1_ISR (isr_usart1)
177 #define UART_1_DMA_ISR (isr_dma2_stream7)
178 #define UART_2_ISR (isr_usart3)
179 #define UART_2_DMA_ISR (isr_dma1_stream3)
180 
181 /* deduct number of defined UART interfaces */
182 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
183 
192 static const uint8_t spi_divtable[2][5] = {
193  { /* for APB1 @ 42000000Hz */
194  7, /* -> 164062Hz */
195  6, /* -> 328125Hz */
196  4, /* -> 1312500Hz */
197  2, /* -> 5250000Hz */
198  1 /* -> 10500000Hz */
199  },
200  { /* for APB2 @ 84000000Hz */
201  7, /* -> 328125Hz */
202  7, /* -> 328125Hz */
203  5, /* -> 1312500Hz */
204  3, /* -> 5250000Hz */
205  2 /* -> 10500000Hz */
206  }
207 };
208 
209 static const spi_conf_t spi_config[] = {
210  {
211  .dev = SPI1,
212  .mosi_pin = GPIO_PIN(PORT_A, 7),
213  .miso_pin = GPIO_PIN(PORT_A, 6),
214  .sclk_pin = GPIO_PIN(PORT_A, 5),
215  .cs_pin = GPIO_PIN(PORT_A, 4),
216  .af = GPIO_AF5,
217  .rccmask = RCC_APB2ENR_SPI1EN,
218  .apbbus = APB2
219  }
220 };
221 
222 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
223 
229 #define I2C_NUMOF (1U)
230 #define I2C_0_EN 1
231 #define I2C_IRQ_PRIO 1
232 #define I2C_APBCLK (CLOCK_APB1)
233 
234 /* I2C 0 device configuration */
235 #define I2C_0_DEV I2C1
236 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
237 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
238 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
239 #define I2C_0_EVT_ISR isr_i2c1_ev
240 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
241 #define I2C_0_ERR_ISR isr_i2c1_er
242 /* I2C 0 pin configuration */
243 #define I2C_0_SCL_PORT GPIOB
244 #define I2C_0_SCL_PIN 6
245 #define I2C_0_SCL_AF 4
246 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
247 #define I2C_0_SDA_PORT GPIOB
248 #define I2C_0_SDA_PIN 7
249 #define I2C_0_SDA_AF 4
250 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
251 
252 #ifdef __cplusplus
253 }
254 #endif
255 
256 #endif /* PERIPH_CONF_H */
257 
use alternate function 7
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
gpio_t pin
pin connected to the line
use alternate function 3
PWM configuration structure.
LPC_CTxxBx_Type * dev
PWM device.
use alternate function 5
UART device configuration.
CPU specific DAC configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
cc2538_ssi_t * dev
SSI device.