boards/msbiot/include/periph_conf.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2014 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 #define CLOCK_HSE (16000000U) /* external oscillator */
33 #define CLOCK_CORECLOCK (168000000U) /* desired core clock frequency */
34 
35 /* the actual PLL values are automatically generated */
36 #define CLOCK_PLL_M (CLOCK_HSE / 1000000)
37 #define CLOCK_PLL_N ((CLOCK_CORECLOCK / 1000000) * 2)
38 #define CLOCK_PLL_P (2U)
39 #define CLOCK_PLL_Q (CLOCK_PLL_N / 48)
40 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
41 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
42 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
43 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS
44 
45 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
46 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
47 #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
48 #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
49 
55 static const timer_conf_t timer_config[] = {
56  {
57  .dev = TIM2,
58  .max = 0xffffffff,
59  .rcc_mask = RCC_APB1ENR_TIM2EN,
60  .bus = APB1,
61  .irqn = TIM2_IRQn
62  },
63  {
64  .dev = TIM5,
65  .max = 0xffffffff,
66  .rcc_mask = RCC_APB1ENR_TIM5EN,
67  .bus = APB1,
68  .irqn = TIM5_IRQn
69  }
70 };
71 
72 #define TIMER_0_ISR isr_tim2
73 #define TIMER_1_ISR isr_tim5
74 
75 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
76 
82 static const pwm_conf_t pwm_config[] = {
83  {
84  .dev = TIM11,
85  .rcc_mask = RCC_APB2ENR_TIM11EN,
86  .chan = { { .pin = GPIO_PIN(PORT_B, 9), .cc_chan = 0 },
87  { .pin = GPIO_UNDEF, .cc_chan = 0 },
88  { .pin = GPIO_UNDEF, .cc_chan = 0 },
89  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
90  .af = GPIO_AF3,
91  .bus = APB2
92  }
93 };
94 
95 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
96 
105 #define ADC_CONFIG { \
106  {GPIO_PIN(PORT_B, 0), 0, 8}, \
107  {GPIO_PIN(PORT_B, 1), 0, 9} \
108 }
109 
110 #define ADC_NUMOF (2)
111 
120 #define DAC_CONFIG { \
121  {GPIO_PIN(PORT_A, 4), 0}, \
122  {GPIO_PIN(PORT_A, 5), 1} \
123 }
124 
125 #define DAC_NUMOF (2)
126 
132 static const uart_conf_t uart_config[] = {
133  {
134  .dev = USART2,
135  .rcc_mask = RCC_APB1ENR_USART2EN,
136  .rx_pin = GPIO_PIN(PORT_A, 3),
137  .tx_pin = GPIO_PIN(PORT_A, 2),
138  .rx_af = GPIO_AF7,
139  .tx_af = GPIO_AF7,
140  .bus = APB1,
141  .irqn = USART2_IRQn,
142 #ifdef UART_USE_DMA
143  .dma_stream = 6,
144  .dma_chan = 4
145 #endif
146  },
147  {
148  .dev = USART1,
149  .rcc_mask = RCC_APB2ENR_USART1EN,
150  .rx_pin = GPIO_PIN(PORT_A, 10),
151  .tx_pin = GPIO_PIN(PORT_A, 9),
152  .rx_af = GPIO_AF7,
153  .tx_af = GPIO_AF7,
154  .bus = APB2,
155  .irqn = USART1_IRQn,
156 #ifdef UART_USE_DMA
157  .dma_stream = 15,
158  .dma_chan = 4
159 #endif
160  },
161  {
162  .dev = USART3,
163  .rcc_mask = RCC_APB1ENR_USART3EN,
164  .rx_pin = GPIO_PIN(PORT_D, 9),
165  .tx_pin = GPIO_PIN(PORT_D, 8),
166  .rx_af = GPIO_AF7,
167  .tx_af = GPIO_AF7,
168  .bus = APB1,
169  .irqn = USART3_IRQn,
170 #ifdef UART_USE_DMA
171  .dma_stream = 3,
172  .dma_chan = 4
173 #endif
174  },
175 };
176 
177 /* assign ISR vector names */
178 #define UART_0_ISR (isr_usart2)
179 #define UART_0_DMA_ISR (isr_dma1_stream6)
180 #define UART_1_ISR (isr_usart1)
181 #define UART_1_DMA_ISR (isr_dma2_stream7)
182 #define UART_2_ISR (isr_usart3)
183 #define UART_2_DMA_ISR (isr_dma1_stream3)
184 
185 /* deduct number of defined UART interfaces */
186 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
187 
196 static const uint8_t spi_divtable[2][5] = {
197  { /* for APB1 @ 42000000Hz */
198  7, /* -> 164062Hz */
199  6, /* -> 328125Hz */
200  4, /* -> 1312500Hz */
201  2, /* -> 5250000Hz */
202  1 /* -> 10500000Hz */
203  },
204  { /* for APB2 @ 84000000Hz */
205  7, /* -> 328125Hz */
206  7, /* -> 328125Hz */
207  5, /* -> 1312500Hz */
208  3, /* -> 5250000Hz */
209  2 /* -> 10500000Hz */
210  }
211 };
212 
213 static const spi_conf_t spi_config[] = {
214  {
215  .dev = SPI1,
216  .mosi_pin = GPIO_PIN(PORT_A, 7),
217  .miso_pin = GPIO_PIN(PORT_A, 6),
218  .sclk_pin = GPIO_PIN(PORT_A, 5),
219  .cs_pin = GPIO_PIN(PORT_A, 4),
220  .af = GPIO_AF5,
221  .rccmask = RCC_APB2ENR_SPI1EN,
222  .apbbus = APB2
223  }
224 };
225 
226 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
227 
233 #define I2C_NUMOF (1U)
234 #define I2C_0_EN 1
235 #define I2C_IRQ_PRIO 1
236 #define I2C_APBCLK (CLOCK_APB1)
237 
238 /* I2C 0 device configuration */
239 #define I2C_0_DEV I2C1
240 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
241 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
242 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
243 #define I2C_0_EVT_ISR isr_i2c1_ev
244 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
245 #define I2C_0_ERR_ISR isr_i2c1_er
246 /* I2C 0 pin configuration */
247 #define I2C_0_SCL_PORT GPIOB
248 #define I2C_0_SCL_PIN 6
249 #define I2C_0_SCL_AF 4
250 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
251 #define I2C_0_SDA_PORT GPIOB
252 #define I2C_0_SDA_PIN 7
253 #define I2C_0_SDA_AF 4
254 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
255 
256 #ifdef __cplusplus
257 }
258 #endif
259 
260 #endif /* PERIPH_CONF_H */
261 
use alternate function 7
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 3
PWM configuration structure.
LPC_CTxxBx_Type * dev
PWM device.
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
cc2538_ssi_t * dev
SSI device.