boards/msbiot/include/periph_conf.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2014 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
35 /* give the target core clock (HCLK) frequency [in Hz],
36  * maximum: 168MHz */
37 #define CLOCK_CORECLOCK (168000000U)
38 /* 0: no external high speed crystal available
39  * else: actual crystal frequency [in Hz] */
40 #define CLOCK_HSE (16000000U)
41 /* 0: no external low speed crystal available,
42  * 1: external crystal available (always 32.768kHz) */
43 #define CLOCK_LSE (0)
44 /* peripheral clock setup */
45 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
46 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
47 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */
48 #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
49 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */
50 #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
51 
52 /* Main PLL factors */
53 #define CLOCK_PLL_M (8)
54 #define CLOCK_PLL_N (168)
55 #define CLOCK_PLL_P (2)
56 #define CLOCK_PLL_Q (7)
57 
63 static const timer_conf_t timer_config[] = {
64  {
65  .dev = TIM2,
66  .max = 0xffffffff,
67  .rcc_mask = RCC_APB1ENR_TIM2EN,
68  .bus = APB1,
69  .irqn = TIM2_IRQn
70  },
71  {
72  .dev = TIM5,
73  .max = 0xffffffff,
74  .rcc_mask = RCC_APB1ENR_TIM5EN,
75  .bus = APB1,
76  .irqn = TIM5_IRQn
77  }
78 };
79 
80 #define TIMER_0_ISR isr_tim2
81 #define TIMER_1_ISR isr_tim5
82 
83 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
84 
90 static const pwm_conf_t pwm_config[] = {
91  {
92  .dev = TIM11,
93  .rcc_mask = RCC_APB2ENR_TIM11EN,
94  .chan = { { .pin = GPIO_PIN(PORT_B, 9), .cc_chan = 0 },
95  { .pin = GPIO_UNDEF, .cc_chan = 0 },
96  { .pin = GPIO_UNDEF, .cc_chan = 0 },
97  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
98  .af = GPIO_AF3,
99  .bus = APB2
100  }
101 };
102 
103 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
104 
113 #define ADC_CONFIG { \
114  {GPIO_PIN(PORT_B, 0), 0, 8}, \
115  {GPIO_PIN(PORT_B, 1), 0, 9} \
116 }
117 
118 #define ADC_NUMOF (2)
119 
125 static const dac_conf_t dac_config[] = {
126  { .pin = GPIO_PIN(PORT_A, 4), .chan = 0 },
127  { .pin = GPIO_PIN(PORT_A, 5), .chan = 1 }
128 };
129 
130 #define DAC_NUMOF (sizeof(dac_config) / sizeof(dac_config[0]))
131 
137 static const uart_conf_t uart_config[] = {
138  {
139  .dev = USART2,
140  .rcc_mask = RCC_APB1ENR_USART2EN,
141  .rx_pin = GPIO_PIN(PORT_A, 3),
142  .tx_pin = GPIO_PIN(PORT_A, 2),
143  .rx_af = GPIO_AF7,
144  .tx_af = GPIO_AF7,
145  .bus = APB1,
146  .irqn = USART2_IRQn,
147 #ifdef UART_USE_DMA
148  .dma_stream = 6,
149  .dma_chan = 4
150 #endif
151  },
152  {
153  .dev = USART1,
154  .rcc_mask = RCC_APB2ENR_USART1EN,
155  .rx_pin = GPIO_PIN(PORT_A, 10),
156  .tx_pin = GPIO_PIN(PORT_A, 9),
157  .rx_af = GPIO_AF7,
158  .tx_af = GPIO_AF7,
159  .bus = APB2,
160  .irqn = USART1_IRQn,
161 #ifdef UART_USE_DMA
162  .dma_stream = 15,
163  .dma_chan = 4
164 #endif
165  },
166  {
167  .dev = USART3,
168  .rcc_mask = RCC_APB1ENR_USART3EN,
169  .rx_pin = GPIO_PIN(PORT_D, 9),
170  .tx_pin = GPIO_PIN(PORT_D, 8),
171  .rx_af = GPIO_AF7,
172  .tx_af = GPIO_AF7,
173  .bus = APB1,
174  .irqn = USART3_IRQn,
175 #ifdef UART_USE_DMA
176  .dma_stream = 3,
177  .dma_chan = 4
178 #endif
179  },
180 };
181 
182 /* assign ISR vector names */
183 #define UART_0_ISR (isr_usart2)
184 #define UART_0_DMA_ISR (isr_dma1_stream6)
185 #define UART_1_ISR (isr_usart1)
186 #define UART_1_DMA_ISR (isr_dma2_stream7)
187 #define UART_2_ISR (isr_usart3)
188 #define UART_2_DMA_ISR (isr_dma1_stream3)
189 
190 /* deduct number of defined UART interfaces */
191 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
192 
201 static const uint8_t spi_divtable[2][5] = {
202  { /* for APB1 @ 42000000Hz */
203  7, /* -> 164062Hz */
204  6, /* -> 328125Hz */
205  4, /* -> 1312500Hz */
206  2, /* -> 5250000Hz */
207  1 /* -> 10500000Hz */
208  },
209  { /* for APB2 @ 84000000Hz */
210  7, /* -> 328125Hz */
211  7, /* -> 328125Hz */
212  5, /* -> 1312500Hz */
213  3, /* -> 5250000Hz */
214  2 /* -> 10500000Hz */
215  }
216 };
217 
218 static const spi_conf_t spi_config[] = {
219  {
220  .dev = SPI1,
221  .mosi_pin = GPIO_PIN(PORT_A, 7),
222  .miso_pin = GPIO_PIN(PORT_A, 6),
223  .sclk_pin = GPIO_PIN(PORT_A, 5),
224  .cs_pin = GPIO_PIN(PORT_A, 4),
225  .af = GPIO_AF5,
226  .rccmask = RCC_APB2ENR_SPI1EN,
227  .apbbus = APB2
228  }
229 };
230 
231 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
232 
238 #define I2C_NUMOF (1U)
239 #define I2C_0_EN 1
240 #define I2C_IRQ_PRIO 1
241 #define I2C_APBCLK (CLOCK_APB1)
242 
243 /* I2C 0 device configuration */
244 #define I2C_0_DEV I2C1
245 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
246 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
247 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
248 #define I2C_0_EVT_ISR isr_i2c1_ev
249 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
250 #define I2C_0_ERR_ISR isr_i2c1_er
251 /* I2C 0 pin configuration */
252 #define I2C_0_SCL_PORT GPIOB
253 #define I2C_0_SCL_PIN 6
254 #define I2C_0_SCL_AF 4
255 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
256 #define I2C_0_SDA_PORT GPIOB
257 #define I2C_0_SDA_PIN 7
258 #define I2C_0_SDA_AF 4
259 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
260 
261 #ifdef __cplusplus
262 }
263 #endif
264 
265 #endif /* PERIPH_CONF_H */
266 
use alternate function 7
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
gpio_t pin
pin connected to the line
use alternate function 3
PWM configuration structure.
NRF_TIMER_Type * dev
timer device
use alternate function 5
Tcc * dev
TCC device to use.
UART device configuration.
DAC line configuration data.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI module configuration options.
Timer configuration.
cc2538_ssi_t * dev
SSI device.