boards/maple-mini/include/periph_conf.h
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1 /*
2  * Copyright (C) 2016 Frits Kuipers
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 /* high speed clock configuration:
33  * 0 := use internal HSI oscillator (always 8MHz)
34  * HSE frequency value := use external HSE oscillator with given freq [in Hz]
35  * must be 4000000 <= value <= 16000000 */
36 #define CLOCK_HSE (8000000U)
37 /* low speed clock configuration:
38  * 0 := use internal LSI oscillator (~40kHz)
39  * 1 := use extern LSE oscillator, always 32.768kHz */
40 #define CLOCK_LSE (0)
41 /* targeted system clock speed [in Hz], must be <= 72MHz */
42 #define CLOCK_CORECLOCK (72000000U)
43 /* PLL configuration, set both values to zero to disable PLL usage. The values
44  * must be set to satisfy the following equation:
45  * CORECLOCK := CLOCK_SOURCE / PLL_DIV * PLL_MUL
46  * with
47  * 1 <= CLOCK_PLL_DIV <= 2
48  * 2 <= CLOCK_PLL_MUL <= 17 */
49 #define CLOCK_PLL_DIV (1)
50 #define CLOCK_PLL_MUL (9)
51 /* AHB and APBx bus clock configuration, keep in mind the following constraints:
52  * ABP1 <= 36MHz
53  */
54 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
55 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
56 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
57 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
58 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
59 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
60 
66 #define ADC_NUMOF (0)
67 
73 static const timer_conf_t timer_config[] = {
74  {
75  .dev = TIM2,
76  .max = 0x0000ffff,
77  .rcc_mask = RCC_APB1ENR_TIM2EN,
78  .bus = APB1,
79  .irqn = TIM2_IRQn
80  },
81  {
82  .dev = TIM3,
83  .max = 0x0000ffff,
84  .rcc_mask = RCC_APB1ENR_TIM3EN,
85  .bus = APB1,
86  .irqn = TIM3_IRQn
87  }
88 };
89 
90 #define TIMER_0_ISR isr_tim2
91 #define TIMER_1_ISR isr_tim3
92 
93 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
94 
100 static const uart_conf_t uart_config[] = {
101  {
102  .dev = USART2,
103  .rcc_mask = RCC_APB1ENR_USART2EN,
104  .rx_pin = GPIO_PIN(PORT_A, 3),
105  .tx_pin = GPIO_PIN(PORT_A, 2),
106  .bus = APB1,
107  .irqn = USART2_IRQn
108  },
109  {
110  .dev = USART1,
111  .rcc_mask = RCC_APB2ENR_USART1EN,
112  .rx_pin = GPIO_PIN(PORT_A, 10),
113  .tx_pin = GPIO_PIN(PORT_A, 9),
114  .bus = APB2,
115  .irqn = USART1_IRQn
116  },
117  {
118  .dev = USART3,
119  .rcc_mask = RCC_APB1ENR_USART3EN,
120  .rx_pin = GPIO_PIN(PORT_B, 11),
121  .tx_pin = GPIO_PIN(PORT_B, 10),
122  .bus = APB1,
123  .irqn = USART3_IRQn
124  }
125 };
126 
127 #define UART_0_ISR isr_usart2
128 #define UART_1_ISR isr_usart1
129 #define UART_2_ISR isr_usart3
130 
131 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
132 
138 #define I2C_NUMOF (2U)
139 #define I2C_0_EN 1
140 #define I2C_1_EN 0
141 #define I2C_IRQ_PRIO 1
142 #define I2C_APBCLK (CLOCK_APB1)
143 
144 /* I2C 0 device configuration */
145 #define I2C_0_DEV I2C1
146 #define I2C_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN)
147 #define I2C_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
148 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
149 #define I2C_0_EVT_ISR isr_i2c1_ev
150 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
151 #define I2C_0_ERR_ISR isr_i2c1_er
152 /* I2C 0 pin configuration */
153 #define I2C_0_SCL_PIN GPIO_PIN(PORT_B, 6) /* D15 */
154 #define I2C_0_SDA_PIN GPIO_PIN(PORT_B, 7) /* D16 */
155 
156 /* I2C 1 device configuration */
157 #define I2C_1_DEV I2C2
158 #define I2C_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C2EN)
159 #define I2C_1_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
160 #define I2C_1_EVT_IRQ I2C2_EV_IRQn
161 #define I2C_1_EVT_ISR isr_i2c2_ev
162 #define I2C_1_ERR_IRQ I2C2_ER_IRQn
163 #define I2C_1_ERR_ISR isr_i2c2_er
164 /* I2C 1 pin configuration */
165 #define I2C_1_SCL_PIN GPIO_PIN(PORT_B, 10) /* D1 */
166 #define I2C_1_SDA_PIN GPIO_PIN(PORT_B, 11) /* D0 */
167 
175 static const uint8_t spi_divtable[2][5] = {
176  { /* for APB1 @ 36000000Hz */
177  7, /* -> 140625Hz */
178  6, /* -> 281250Hz */
179  4, /* -> 1125000Hz */
180  2, /* -> 4500000Hz */
181  1 /* -> 9000000Hz */
182  },
183  { /* for APB2 @ 72000000Hz */
184  7, /* -> 281250Hz */
185  7, /* -> 281250Hz */
186  5, /* -> 1125000Hz */
187  3, /* -> 4500000Hz */
188  2 /* -> 9000000Hz */
189  }
190 };
191 
196 static const spi_conf_t spi_config[] = {
197  {
198  .dev = SPI1,
199  .mosi_pin = GPIO_PIN(PORT_A, 7),
200  .miso_pin = GPIO_PIN(PORT_A, 6),
201  .sclk_pin = GPIO_PIN(PORT_A, 5),
202  .cs_pin = GPIO_UNDEF,
203  .rccmask = RCC_APB2ENR_SPI1EN,
204  .apbbus = APB2
205  },
206  {
207  .dev = SPI2,
208  .mosi_pin = GPIO_PIN(PORT_B, 15),
209  .miso_pin = GPIO_PIN(PORT_B, 14),
210  .sclk_pin = GPIO_PIN(PORT_B, 13),
211  .cs_pin = GPIO_UNDEF,
212  .rccmask = RCC_APB1ENR_SPI2EN,
213  .apbbus = APB1
214  }
215 };
216 
217 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
218 
220 #ifdef __cplusplus
221 }
222 #endif
223 
224 #endif /* PERIPH_CONF_H */
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
NRF_TIMER_Type * dev
timer device
UART device configuration.
static const uint8_t spi_divtable[2][5]
Shared SPI clock div table.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI module configuration options.
Timer configuration.
cc2538_ssi_t * dev
SSI device.