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boards/maple-mini/include/periph_conf.h
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1 /*
2  * Copyright (C) 2016 Frits Kuipers
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 #define CLOCK_HSE (8000000U) /* external oscillator */
33 #define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
34 
35 /* the actual PLL values are automatically generated */
36 #define CLOCK_PLL_DIV (1)
37 #define CLOCK_PLL_MUL CLOCK_CORECLOCK / CLOCK_HSE
38 
39 /* AHB, APB1, APB2 dividers */
40 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
41 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
42 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
43 
44 /* Bus clocks */
45 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
46 #define CLOCK_APB2 (CLOCK_CORECLOCK)
47 
48 /* Flash latency */
49 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_2 /* for >= 72 MHz */
50 
56 #define ADC_NUMOF (0)
57 
63 #define DAC_NUMOF (0)
64 
70 static const timer_conf_t timer_config[] = {
71  {
72  .dev = TIM2,
73  .max = 0x0000ffff,
74  .rcc_mask = RCC_APB1ENR_TIM2EN,
75  .bus = APB1,
76  .irqn = TIM2_IRQn
77  },
78  {
79  .dev = TIM3,
80  .max = 0x0000ffff,
81  .rcc_mask = RCC_APB1ENR_TIM3EN,
82  .bus = APB1,
83  .irqn = TIM3_IRQn
84  }
85 };
86 
87 #define TIMER_0_ISR isr_tim2
88 #define TIMER_1_ISR isr_tim3
89 
90 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
91 
97 static const uart_conf_t uart_config[] = {
98  {
99  .dev = USART2,
100  .rcc_mask = RCC_APB1ENR_USART2EN,
101  .rx_pin = GPIO_PIN(PORT_A, 3),
102  .tx_pin = GPIO_PIN(PORT_A, 2),
103  .bus = APB1,
104  .irqn = USART2_IRQn
105  },
106  {
107  .dev = USART1,
108  .rcc_mask = RCC_APB2ENR_USART1EN,
109  .rx_pin = GPIO_PIN(PORT_A, 10),
110  .tx_pin = GPIO_PIN(PORT_A, 9),
111  .bus = APB2,
112  .irqn = USART1_IRQn
113  },
114  {
115  .dev = USART3,
116  .rcc_mask = RCC_APB1ENR_USART3EN,
117  .rx_pin = GPIO_PIN(PORT_B, 11),
118  .tx_pin = GPIO_PIN(PORT_B, 10),
119  .bus = APB1,
120  .irqn = USART3_IRQn
121  }
122 };
123 
124 #define UART_0_ISR isr_usart2
125 #define UART_1_ISR isr_usart1
126 #define UART_2_ISR isr_usart3
127 
128 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
129 
135 #define I2C_NUMOF (2U)
136 #define I2C_0_EN 1
137 #define I2C_1_EN 0
138 #define I2C_IRQ_PRIO 1
139 #define I2C_APBCLK (36000000U)
140 
141 /* I2C 0 device configuration */
142 #define I2C_0_DEV I2C1
143 #define I2C_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN)
144 #define I2C_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
145 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
146 #define I2C_0_EVT_ISR isr_i2c1_ev
147 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
148 #define I2C_0_ERR_ISR isr_i2c1_er
149 /* I2C 0 pin configuration */
150 #define I2C_0_SCL_PIN GPIO_PIN(PORT_B, 6) /* D15 */
151 #define I2C_0_SDA_PIN GPIO_PIN(PORT_B, 7) /* D16 */
152 
153 /* I2C 1 device configuration */
154 #define I2C_1_DEV I2C2
155 #define I2C_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C2EN)
156 #define I2C_1_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
157 #define I2C_1_EVT_IRQ I2C2_EV_IRQn
158 #define I2C_1_EVT_ISR isr_i2c2_ev
159 #define I2C_1_ERR_IRQ I2C2_ER_IRQn
160 #define I2C_1_ERR_ISR isr_i2c2_er
161 /* I2C 1 pin configuration */
162 #define I2C_1_SCL_PIN GPIO_PIN(PORT_B, 10) /* D1 */
163 #define I2C_1_SDA_PIN GPIO_PIN(PORT_B, 11) /* D0 */
164 
172 static const uint8_t spi_divtable[2][5] = {
173  { /* for APB1 @ 36000000Hz */
174  7, /* -> 140625Hz */
175  6, /* -> 281250Hz */
176  4, /* -> 1125000Hz */
177  2, /* -> 4500000Hz */
178  1 /* -> 9000000Hz */
179  },
180  { /* for APB2 @ 72000000Hz */
181  7, /* -> 281250Hz */
182  7, /* -> 281250Hz */
183  5, /* -> 1125000Hz */
184  3, /* -> 4500000Hz */
185  2 /* -> 9000000Hz */
186  }
187 };
188 
193 static const spi_conf_t spi_config[] = {
194  {
195  .dev = SPI1,
196  .mosi_pin = GPIO_PIN(PORT_A, 7),
197  .miso_pin = GPIO_PIN(PORT_A, 6),
198  .sclk_pin = GPIO_PIN(PORT_A, 5),
199  .cs_pin = GPIO_UNDEF,
200  .rccmask = RCC_APB2ENR_SPI1EN,
201  .apbbus = APB2
202  },
203  {
204  .dev = SPI2,
205  .mosi_pin = GPIO_PIN(PORT_B, 15),
206  .miso_pin = GPIO_PIN(PORT_B, 14),
207  .sclk_pin = GPIO_PIN(PORT_B, 13),
208  .cs_pin = GPIO_UNDEF,
209  .rccmask = RCC_APB1ENR_SPI2EN,
210  .apbbus = APB1
211  }
212 };
213 
214 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
215 
217 #ifdef __cplusplus
218 }
219 #endif
220 
221 #endif /* PERIPH_CONF_H */
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
UART device configuration.
static const uint8_t spi_divtable[2][5]
Shared SPI clock div table.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
cc2538_ssi_t * dev
SSI device.