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periph_conf.h
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1/*
2 * Copyright (C) 2019 Inria
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
19#ifndef PERIPH_CONF_H
20#define PERIPH_CONF_H
21
22/* Add specific clock configuration (HSE, LSE) for this board here */
23#ifndef CONFIG_BOARD_HAS_LSE
24#define CONFIG_BOARD_HAS_LSE 1
25#endif
26
27#include "periph_cpu.h"
28#include "clk_conf.h"
29#include "cfg_rtt_default.h"
30#include "cfg_timer_tim2.h"
31
32#ifdef __cplusplus
33extern "C" {
34#endif
35
40static const dma_conf_t dma_config[] = {
41 { .stream = 1 }, /* channel 2 */
42 { .stream = 2 }, /* channel 3 */
43 { .stream = 3 }, /* channel 4 */
44 { .stream = 4 }, /* channel 5 */
45 { .stream = 5 }, /* channel 6 */
46};
47
48#define DMA_SHARED_ISR_0 isr_dma1_channel2_3
49#define DMA_SHARED_ISR_0_STREAMS { 0, 1 } /* Indexes 0 and 1 of dma_config share the same isr */
50#define DMA_SHARED_ISR_1 isr_dma1_channel4_5_6_7
51#define DMA_SHARED_ISR_1_STREAMS { 2, 3, 4 } /* Indexes 2, 3 and 4 of dma_config share the same isr */
52
53#define DMA_NUMOF ARRAY_SIZE(dma_config)
60static const uart_conf_t uart_config[] = {
61 {
62 .dev = USART1,
63 .rcc_mask = RCC_APB2ENR_USART1EN,
64 .rx_pin = GPIO_PIN(PORT_A, 10),
65 .tx_pin = GPIO_PIN(PORT_A, 9),
66 .rx_af = GPIO_AF4,
67 .tx_af = GPIO_AF4,
68 .bus = APB2,
69 .irqn = USART1_IRQn,
70 .type = STM32_USART,
71 .clk_src = 0, /* Use APB clock */
72#ifdef MODULE_PERIPH_DMA
73 .dma = 0,
74 .dma_chan = 3,
75#endif
76 },
77 {
78 .dev = USART2,
79 .rcc_mask = RCC_APB1ENR_USART2EN,
80 .rx_pin = GPIO_PIN(PORT_A, 3),
81 .tx_pin = GPIO_PIN(PORT_A, 2),
82 .rx_af = GPIO_AF4,
83 .tx_af = GPIO_AF4,
84 .bus = APB1,
85 .irqn = USART2_IRQn,
86 .type = STM32_USART,
87 .clk_src = 0, /* Use APB clock */
88#ifdef MODULE_PERIPH_DMA
89 .dma = 2,
90 .dma_chan = 4,
91#endif
92 },
93};
94
95#define UART_0_ISR (isr_usart1)
96#define UART_1_ISR (isr_usart2)
97
98#define UART_NUMOF ARRAY_SIZE(uart_config)
105static const spi_conf_t spi_config[] = {
106 {
107 .dev = SPI1, /* connected to SX1276 */
108 .mosi_pin = GPIO_PIN(PORT_A, 7),
109 .miso_pin = GPIO_PIN(PORT_A, 6),
110 .sclk_pin = GPIO_PIN(PORT_A, 5),
111 .cs_pin = SPI_CS_UNDEF,
112 .mosi_af = GPIO_AF0,
113 .miso_af = GPIO_AF0,
114 .sclk_af = GPIO_AF0,
115 .cs_af = GPIO_AF0,
116 .rccmask = RCC_APB2ENR_SPI1EN,
117 .apbbus = APB2,
118#ifdef MODULE_PERIPH_DMA
119 .tx_dma = 1,
120 .tx_dma_chan = 1,
121 .rx_dma = 0,
122 .rx_dma_chan = 1,
123#endif
124 },
125};
126
127#define SPI_NUMOF ARRAY_SIZE(spi_config)
134static const i2c_conf_t i2c_config[] = {
135 {
136 .dev = I2C1,
137 .speed = I2C_SPEED_NORMAL,
138 .scl_pin = GPIO_PIN(PORT_B, 6),
139 .sda_pin = GPIO_PIN(PORT_B, 7),
140 .scl_af = GPIO_AF4,
141 .sda_af = GPIO_AF4,
142 .bus = APB1,
143 .rcc_mask = RCC_APB1ENR_I2C1EN,
144 .irqn = I2C1_IRQn
145 }
146};
147
148#define I2C_0_ISR isr_i2c1
149
150#define I2C_NUMOF ARRAY_SIZE(i2c_config)
153#ifdef __cplusplus
154}
155#endif
156
157#endif /* PERIPH_CONF_H */
@ PORT_B
port B
Definition periph_cpu.h:48
@ PORT_A
port A
Definition periph_cpu.h:47
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:278
Common configuration for STM32 Timer peripheral based on TIM2.
@ GPIO_AF4
use alternate function 4
Definition cpu_gpio.h:106
@ GPIO_AF0
use alternate function 0
Definition cpu_gpio.h:102
@ STM32_USART
STM32 USART module type.
Definition cpu_uart.h:38
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition periph_cpu.h:363
@ APB1
Advanced Peripheral Bus 1
Definition periph_cpu.h:79
@ APB2
Advanced Peripheral Bus 2
Definition periph_cpu.h:80
DMA configuration.
Definition cpu_dma.h:32
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition cpu_dma.h:55
I2C configuration structure.
Definition periph_cpu.h:299
TWI_t * dev
Pointer to hardware module registers.
Definition periph_cpu.h:300
SPI device configuration.
Definition periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:338
UART device configuration.
Definition periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:219