periph_conf.h File Reference

Support for the Lobaro lorabox with stm32l151cb. More...

Detailed Description

#include "periph_cpu.h"
#include "cfg_timer_tim2.h"
+ Include dependency graph for periph_conf.h:

Go to the source code of this file.

xtimer configuration

#define XTIMER_WIDTH   (16)
 
#define XTIMER_BACKOFF   (50)
 
#define XTIMER_ISR_BACKOFF   (40)
 

Clock system configuration

#define CLOCK_HSI   (16000000U) /* frequency of internal oscillator */
 
#define CLOCK_CORECLOCK   (32000000U) /* targeted core clock frequency */
 
#define CLOCK_LSE   (1)
 
#define CLOCK_PLL_DIV   RCC_CFGR_PLLDIV2
 
#define CLOCK_PLL_MUL   RCC_CFGR_PLLMUL4
 
#define CLOCK_AHB_DIV   RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
 
#define CLOCK_APB2_DIV   RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
 
#define CLOCK_APB1_DIV   RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
 
#define CLOCK_FLASH_LATENCY   FLASH_ACR_LATENCY
 
#define CLOCK_AHB   (CLOCK_CORECLOCK / 1)
 
#define CLOCK_APB2   (CLOCK_CORECLOCK / 1)
 
#define CLOCK_APB1   (CLOCK_CORECLOCK / 1)
 

UART configuration

#define UART_0_ISR   (isr_usart1)
 
#define UART_1_ISR   (isr_usart2)
 
#define UART_NUMOF   ARRAY_SIZE(uart_config)
 
static const uart_conf_t uart_config []
 

PWM configuration

#define PWM_NUMOF   0
 

SPI configuration

Note
The spi_divtable is auto-generated from cpu/stm32_common/dist/spi_divtable/spi_divtable.c
#define SPI_NUMOF   ARRAY_SIZE(spi_config)
 
static const uint8_t spi_divtable [2][5]
 
static const spi_conf_t spi_config []
 

I2C configuration

#define I2C_0_ISR   isr_i2c1_ev
 
#define I2C_NUMOF   ARRAY_SIZE(i2c_config)
 
static const i2c_conf_t i2c_config []
 

Variable Documentation

◆ i2c_config

const i2c_conf_t i2c_config[]
static
Initial value:
= {
{
.dev = I2C1,
.speed = I2C_SPEED_NORMAL,
.scl_pin = GPIO_PIN(PORT_B, 8),
.sda_pin = GPIO_PIN(PORT_B, 9),
.scl_af = GPIO_AF4,
.sda_af = GPIO_AF4,
.bus = APB1,
.rcc_mask = RCC_APB1ENR_I2C1EN,
.clk = CLOCK_APB1,
.irqn = I2C1_EV_IRQn
}
}
use alternate function 4
APB1 bus.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
normal mode: ~100kbit/s
Definition: periph_cpu.h:116
port B
Definition: periph_cpu.h:37

Definition at line 168 of file periph_conf.h.

◆ spi_config

const spi_conf_t spi_config[]
static
Initial value:
= {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_PIN(PORT_B, 0),
.af = GPIO_AF5,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
},
{
.dev = SPI2,
.mosi_pin = GPIO_PIN(PORT_B, 14),
.miso_pin = GPIO_PIN(PORT_B, 15),
.sclk_pin = GPIO_PIN(PORT_B, 13),
.cs_pin = GPIO_PIN(PORT_B, 12),
.af = GPIO_AF5,
.rccmask = RCC_APB1ENR_SPI2EN,
.apbbus = APB1
}
}
APB1 bus.
port A
Definition: periph_cpu.h:36
APB2 bus.
use alternate function 5
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
port B
Definition: periph_cpu.h:37

Definition at line 138 of file periph_conf.h.

◆ spi_divtable

const uint8_t spi_divtable[2][5]
static
Initial value:
= {
{
7,
5,
4,
2,
1
},
{
7,
5,
4,
2,
1
}
}

Definition at line 121 of file periph_conf.h.

◆ uart_config

const uart_conf_t uart_config[]
static
Initial value:
= {
{
.dev = USART1,
.rcc_mask = RCC_APB2ENR_USART1EN,
.rx_pin = GPIO_PIN(PORT_A, 10),
.tx_pin = GPIO_PIN(PORT_A, 9),
.rx_af = GPIO_AF7,
.tx_af = GPIO_AF7,
.bus = APB2,
.irqn = USART1_IRQn
},
{
.dev = USART2,
.rcc_mask = RCC_APB1ENR_USART2EN,
.rx_pin = GPIO_PIN(PORT_A, 3),
.tx_pin = GPIO_PIN(PORT_A, 2),
.rx_af = GPIO_AF7,
.tx_af = GPIO_AF7,
.bus = APB1,
.irqn = USART2_IRQn
}
}
use alternate function 7
APB1 bus.
port A
Definition: periph_cpu.h:36
APB2 bus.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35

Definition at line 78 of file periph_conf.h.