boards/frdm-k64f/include/periph_conf.h
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1 /*
2  * Copyright (C) 2014 Freie Universit├Ąt Berlin
3  * Copyright (C) 2015 PHYTEC Messtechnik GmbH
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser General
6  * Public License v2.1. See the file LICENSE in the top level directory for more
7  * details.
8  */
9 
20 #ifndef PERIPH_CONF_H
21 #define PERIPH_CONF_H
22 
23 #include "periph_cpu.h"
24 
25 #ifdef __cplusplus
26 extern "C"
27 {
28 #endif
29 
34 #define KINETIS_CPU_USE_MCG 1
35 
36 #define KINETIS_MCG_USE_ERC 1
37 #define KINETIS_MCG_USE_PLL 1
38 #define KINETIS_MCG_DCO_RANGE (24000000U)
39 #define KINETIS_MCG_ERC_OSCILLATOR 0
40 #define KINETIS_MCG_ERC_FRDIV 6 /* ERC devider = 1280 */
41 #define KINETIS_MCG_ERC_RANGE 2
42 #define KINETIS_MCG_ERC_FREQ 50000000
43 #define KINETIS_MCG_PLL_PRDIV 19 /* divide factor = 20 */
44 #define KINETIS_MCG_PLL_VDIV0 0 /* multiply factor = 24 */
45 #define KINETIS_MCG_PLL_FREQ 60000000
46 
47 #define CLOCK_CORECLOCK KINETIS_MCG_PLL_FREQ
48 #define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 2)
49 
55 #define PIT_NUMOF (2U)
56 #define PIT_CONFIG { \
57  { \
58  .prescaler_ch = 0, \
59  .count_ch = 1, \
60  }, \
61  { \
62  .prescaler_ch = 2, \
63  .count_ch = 3, \
64  }, \
65  }
66 #define LPTMR_NUMOF (0U)
67 #define LPTMR_CONFIG {}
68 #define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
69 
70 #define PIT_BASECLOCK (CLOCK_BUSCLOCK)
71 #define PIT_ISR_0 isr_pit1
72 #define PIT_ISR_1 isr_pit3
73 #define LPTMR_ISR_0 isr_lptmr0
74 
81 static const uart_conf_t uart_config[] = {
82  {
83  .dev = UART0,
84  .freq = CLOCK_CORECLOCK,
85  .pin_rx = GPIO_PIN(PORT_B, 16),
86  .pin_tx = GPIO_PIN(PORT_B, 17),
87  .pcr_rx = PORT_PCR_MUX(3),
88  .pcr_tx = PORT_PCR_MUX(3),
89  .irqn = UART0_RX_TX_IRQn,
90  .scgc_addr = &SIM->SCGC4,
91  .scgc_bit = SIM_SCGC4_UART0_SHIFT,
92  .mode = UART_MODE_8N1
93  },
94 };
95 
96 #define UART_0_ISR (isr_uart0_rx_tx)
97 
98 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
99 
105 static const adc_conf_t adc_config[] = {
106  /* dev, pin, channel */
107  { ADC0, GPIO_PIN(PORT_B, 10), 14 },
108  { ADC0, GPIO_PIN(PORT_B, 11), 15 },
109  { ADC0, GPIO_PIN(PORT_C, 11), 7 },
110  { ADC0, GPIO_PIN(PORT_C, 10), 6 },
111  { ADC0, GPIO_PIN(PORT_C, 8), 4 },
112  { ADC0, GPIO_PIN(PORT_C, 9), 5 },
113 };
114 
115 #define ADC_NUMOF (sizeof(adc_config) / sizeof(adc_config[0]))
116 
122 #define DAC_CONFIG {}
123 #define DAC_NUMOF 0
124 
130 static const pwm_conf_t pwm_config[] = {
131  {
132  .ftm = FTM0,
133  .chan = {
134  { .pin = GPIO_PIN(PORT_A, 4), .af = 3, .ftm_chan = 6 },
135  { .pin = GPIO_PIN(PORT_A, 2), .af = 3, .ftm_chan = 7 },
136  { .pin = GPIO_PIN(PORT_C, 2), .af = 4, .ftm_chan = 1 },
137  { .pin = GPIO_PIN(PORT_C, 3), .af = 4, .ftm_chan = 2 }
138  },
139  .chan_numof = 4,
140  .ftm_num = 0
141  }
142 };
143 
144 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
145 
158 static const uint32_t spi_clk_config[] = {
159  (
160  SPI_CTAR_PBR(2) | SPI_CTAR_BR(6) | /* -> 93750Hz */
161  SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(5) |
162  SPI_CTAR_PASC(2) | SPI_CTAR_ASC(5) |
163  SPI_CTAR_PDT(2) | SPI_CTAR_DT(5)
164  ),
165  (
166  SPI_CTAR_PBR(2) | SPI_CTAR_BR(4) | /* -> 375000Hz */
167  SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(3) |
168  SPI_CTAR_PASC(2) | SPI_CTAR_ASC(3) |
169  SPI_CTAR_PDT(2) | SPI_CTAR_DT(3)
170  ),
171  (
172  SPI_CTAR_PBR(2) | SPI_CTAR_BR(2) | /* -> 1000000Hz */
173  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(4) |
174  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(4) |
175  SPI_CTAR_PDT(0) | SPI_CTAR_DT(4)
176  ),
177  (
178  SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 5000000Hz */
179  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
180  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
181  SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
182  ),
183  (
184  SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | /* -> 7500000Hz */
185  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(1) |
186  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(1) |
187  SPI_CTAR_PDT(0) | SPI_CTAR_DT(1)
188  )
189 };
190 
191 static const spi_conf_t spi_config[] = {
192  {
193  .dev = SPI0,
194  .pin_miso = GPIO_PIN(PORT_D, 3),
195  .pin_mosi = GPIO_PIN(PORT_D, 2),
196  .pin_clk = GPIO_PIN(PORT_D, 1),
197  .pin_cs = {
198  GPIO_PIN(PORT_D, 0),
199  GPIO_UNDEF,
200  GPIO_UNDEF,
201  GPIO_UNDEF,
202  GPIO_UNDEF
203  },
204  .pcr = GPIO_AF_2,
205  .simmask = SIM_SCGC6_SPI0_MASK
206  }
207 };
208 
209 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
210 
217 #define I2C_NUMOF (1U)
218 #define I2C_CLK CLOCK_CORECLOCK
219 #define I2C_0_EN 1
220 #define I2C_IRQ_PRIO 1
221 /* Low (10 kHz): MUL = 4, SCL divider = 2560, total: 10240 */
222 #define KINETIS_I2C_F_ICR_LOW (0x3D)
223 #define KINETIS_I2C_F_MULT_LOW (2)
224 /* Normal (100 kHz): MUL = 2, SCL divider = 240, total: 480 */
225 #define KINETIS_I2C_F_ICR_NORMAL (0x1F)
226 #define KINETIS_I2C_F_MULT_NORMAL (1)
227 /* Fast (400 kHz): MUL = 1, SCL divider = 128, total: 128 */
228 #define KINETIS_I2C_F_ICR_FAST (0x17)
229 #define KINETIS_I2C_F_MULT_FAST (0)
230 /* Fast plus (1000 kHz): MUL = 1, SCL divider = 48, total: 48 */
231 #define KINETIS_I2C_F_ICR_FAST_PLUS (0x10)
232 #define KINETIS_I2C_F_MULT_FAST_PLUS (0)
233 
234 /* I2C 0 device configuration */
235 #define I2C_0_DEV I2C0
236 #define I2C_0_CLKEN() (SIM->SCGC4 |= (SIM_SCGC4_I2C0_MASK))
237 #define I2C_0_CLKDIS() (SIM->SCGC4 &= ~(SIM_SCGC4_I2C0_MASK))
238 #define I2C_0_IRQ I2C0_IRQn
239 #define I2C_0_IRQ_HANDLER isr_i2c0
240 /* I2C 0 pin configuration */
241 #define I2C_0_PORT PORTE
242 #define I2C_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
243 #define I2C_0_PIN_AF 5
244 #define I2C_0_SDA_PIN 25
245 #define I2C_0_SCL_PIN 24
246 #define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
247 
253 #define GPIO_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
254 
260 #define RTT_NUMOF (1U)
261 #define RTC_NUMOF (1U)
262 #define RTT_DEV RTC
263 #define RTT_IRQ RTC_IRQn
264 #define RTT_IRQ_PRIO 10
265 #define RTT_UNLOCK() (SIM->SCGC6 |= (SIM_SCGC6_RTC_MASK))
266 #define RTT_ISR isr_rtc
267 #define RTT_FREQUENCY (1)
268 #define RTT_MAX_VALUE (0xffffffff)
269 
275 #define KINETIS_RNGA RNG
276 #define HWRNG_CLKEN() (SIM->SCGC6 |= (1 << 9))
277 #define HWRNG_CLKDIS() (SIM->SCGC6 &= ~(1 << 9))
278 
280 #ifdef __cplusplus
281 }
282 #endif
283 
284 #endif /* PERIPH_CONF_H */
285 
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
cc2538_uart_t *const UART0
UART0 Instance.
PWM configuration structure.
use alternate function 2
#define UART_MODE_8N1
8 data bits, no parity, 1 stop bit
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
CPU specific ADC configuration.
cc2538_ssi_t * dev
SSI device.