boards/frdm-k64f/include/periph_conf.h
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1 /*
2  * Copyright (C) 2014 Freie Universit├Ąt Berlin
3  * Copyright (C) 2015 PHYTEC Messtechnik GmbH
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser General
6  * Public License v2.1. See the file LICENSE in the top level directory for more
7  * details.
8  */
9 
20 #ifndef PERIPH_CONF_H
21 #define PERIPH_CONF_H
22 
23 #include "periph_cpu.h"
24 
25 #ifdef __cplusplus
26 extern "C"
27 {
28 #endif
29 
34 static const clock_config_t clock_config = {
35  /*
36  * This configuration results in the system running from the PLL output with
37  * the following clock frequencies:
38  * Core: 60 MHz
39  * Bus: 60 MHz
40  * Flex: 20 MHz
41  * Flash: 20 MHz
42  */
43  .clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) |
44  SIM_CLKDIV1_OUTDIV3(2) | SIM_CLKDIV1_OUTDIV4(2),
45  .default_mode = KINETIS_MCG_MODE_PEE,
46  /* The board has an external RMII (Ethernet) clock which drives the ERC at 50 MHz */
48  .fcrdiv = 0, /* Fast IRC divide by 1 => 4 MHz */
49  .oscsel = 0, /* Use EXTAL for external clock */
50  .clc = 0, /* External load caps on board */
51  .fll_frdiv = 0b111, /* Divide by 1536 => FLL input 32252 Hz */
52  .fll_factor_fei = KINETIS_MCG_FLL_FACTOR_1464, /* FLL freq = 48 MHz */
53  .fll_factor_fee = KINETIS_MCG_FLL_FACTOR_1920, /* FLL freq = 62.5 MHz */
54  .pll_prdiv = 0b10011, /* Divide by 20 */
55  .pll_vdiv = 0b00000, /* Multiply by 24 => PLL freq = 60 MHz */
56  .enable_oscillator = false, /* Use EXTAL directly without OSC0 */
57  .select_fast_irc = true,
58  .enable_mcgirclk = false,
59 };
60 #define CLOCK_CORECLOCK (60000000ul)
61 #define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 1)
62 
68 #define PIT_NUMOF (2U)
69 #define PIT_CONFIG { \
70  { \
71  .prescaler_ch = 0, \
72  .count_ch = 1, \
73  }, \
74  { \
75  .prescaler_ch = 2, \
76  .count_ch = 3, \
77  }, \
78  }
79 #define LPTMR_NUMOF (0U)
80 #define LPTMR_CONFIG {}
81 #define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
82 
83 #define PIT_BASECLOCK (CLOCK_BUSCLOCK)
84 #define PIT_ISR_0 isr_pit1
85 #define PIT_ISR_1 isr_pit3
86 #define LPTMR_ISR_0 isr_lptmr0
87 
94 static const uart_conf_t uart_config[] = {
95  {
96  .dev = UART0,
97  .freq = CLOCK_CORECLOCK,
98  .pin_rx = GPIO_PIN(PORT_B, 16),
99  .pin_tx = GPIO_PIN(PORT_B, 17),
100  .pcr_rx = PORT_PCR_MUX(3),
101  .pcr_tx = PORT_PCR_MUX(3),
102  .irqn = UART0_RX_TX_IRQn,
103  .scgc_addr = &SIM->SCGC4,
104  .scgc_bit = SIM_SCGC4_UART0_SHIFT,
105  .mode = UART_MODE_8N1
106  },
107 };
108 
109 #define UART_0_ISR (isr_uart0_rx_tx)
110 
111 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
112 
118 static const adc_conf_t adc_config[] = {
119  { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 10), .chan = 14 },
120  { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 11), .chan = 15 },
121  { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 11), .chan = 7 },
122  { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 10), .chan = 6 },
123  { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 8), .chan = 4 },
124  { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 9), .chan = 5 }
125 };
126 
127 #define ADC_NUMOF (sizeof(adc_config) / sizeof(adc_config[0]))
128 
134 static const pwm_conf_t pwm_config[] = {
135  {
136  .ftm = FTM0,
137  .chan = {
138  { .pin = GPIO_PIN(PORT_A, 4), .af = 3, .ftm_chan = 6 },
139  { .pin = GPIO_PIN(PORT_A, 2), .af = 3, .ftm_chan = 7 },
140  { .pin = GPIO_PIN(PORT_C, 2), .af = 4, .ftm_chan = 1 },
141  { .pin = GPIO_PIN(PORT_C, 3), .af = 4, .ftm_chan = 2 }
142  },
143  .chan_numof = 4,
144  .ftm_num = 0
145  }
146 };
147 
148 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
149 
162 static const uint32_t spi_clk_config[] = {
163  (
164  SPI_CTAR_PBR(2) | SPI_CTAR_BR(6) | /* -> 93750Hz */
165  SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(5) |
166  SPI_CTAR_PASC(2) | SPI_CTAR_ASC(5) |
167  SPI_CTAR_PDT(2) | SPI_CTAR_DT(5)
168  ),
169  (
170  SPI_CTAR_PBR(2) | SPI_CTAR_BR(4) | /* -> 375000Hz */
171  SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(3) |
172  SPI_CTAR_PASC(2) | SPI_CTAR_ASC(3) |
173  SPI_CTAR_PDT(2) | SPI_CTAR_DT(3)
174  ),
175  (
176  SPI_CTAR_PBR(2) | SPI_CTAR_BR(2) | /* -> 1000000Hz */
177  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(4) |
178  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(4) |
179  SPI_CTAR_PDT(0) | SPI_CTAR_DT(4)
180  ),
181  (
182  SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 5000000Hz */
183  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
184  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
185  SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
186  ),
187  (
188  SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | /* -> 7500000Hz */
189  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(1) |
190  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(1) |
191  SPI_CTAR_PDT(0) | SPI_CTAR_DT(1)
192  )
193 };
194 
195 static const spi_conf_t spi_config[] = {
196  {
197  .dev = SPI0,
198  .pin_miso = GPIO_PIN(PORT_D, 3),
199  .pin_mosi = GPIO_PIN(PORT_D, 2),
200  .pin_clk = GPIO_PIN(PORT_D, 1),
201  .pin_cs = {
202  GPIO_PIN(PORT_D, 0),
203  GPIO_UNDEF,
204  GPIO_UNDEF,
205  GPIO_UNDEF,
206  GPIO_UNDEF
207  },
208  .pcr = GPIO_AF_2,
209  .simmask = SIM_SCGC6_SPI0_MASK
210  }
211 };
212 
213 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
214 
221 #define I2C_NUMOF (1U)
222 #define I2C_0_EN 1
223 /* Low (10 kHz): MUL = 4, SCL divider = 1536, total: 6144 */
224 #define KINETIS_I2C_F_ICR_LOW (0x36)
225 #define KINETIS_I2C_F_MULT_LOW (2)
226 /* Normal (100 kHz): MUL = 2, SCL divider = 320, total: 640 */
227 #define KINETIS_I2C_F_ICR_NORMAL (0x25)
228 #define KINETIS_I2C_F_MULT_NORMAL (1)
229 /* Fast (400 kHz): MUL = 1, SCL divider = 160, total: 160 */
230 #define KINETIS_I2C_F_ICR_FAST (0x1D)
231 #define KINETIS_I2C_F_MULT_FAST (0)
232 /* Fast plus (1000 kHz): MUL = 1, SCL divider = 64, total: 64 */
233 #define KINETIS_I2C_F_ICR_FAST_PLUS (0x12)
234 #define KINETIS_I2C_F_MULT_FAST_PLUS (0)
235 
236 /* I2C 0 device configuration */
237 #define I2C_0_DEV I2C0
238 #define I2C_0_CLKEN() (SIM->SCGC4 |= (SIM_SCGC4_I2C0_MASK))
239 #define I2C_0_CLKDIS() (SIM->SCGC4 &= ~(SIM_SCGC4_I2C0_MASK))
240 #define I2C_0_IRQ I2C0_IRQn
241 #define I2C_0_IRQ_HANDLER isr_i2c0
242 /* I2C 0 pin configuration */
243 #define I2C_0_PORT PORTE
244 #define I2C_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
245 #define I2C_0_PIN_AF 5
246 #define I2C_0_SDA_PIN 25
247 #define I2C_0_SCL_PIN 24
248 #define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
249 
255 #define RTT_NUMOF (1U)
256 #define RTC_NUMOF (1U)
257 #define RTT_DEV RTC
258 #define RTT_IRQ RTC_IRQn
259 #define RTT_IRQ_PRIO 10
260 #define RTT_UNLOCK() (SIM->SCGC6 |= (SIM_SCGC6_RTC_MASK))
261 #define RTT_ISR isr_rtc
262 #define RTT_FREQUENCY (1)
263 #define RTT_MAX_VALUE (0xffffffff)
264 
270 #define KINETIS_RNGA RNG
271 #define HWRNG_CLKEN() (SIM->SCGC6 |= (1 << 9))
272 #define HWRNG_CLKDIS() (SIM->SCGC6 &= ~(1 << 9))
273 
275 #ifdef __cplusplus
276 }
277 #endif
278 
279 #endif /* PERIPH_CONF_H */
280 
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
#define CLOCK_CORECLOCK
Core clock frequency, used by the ARM core and certain hardware modules in Kinetis CPUs...
Definition: mcg.h:137
cc2538_uart_t *const UART0
UART0 Instance.
PWM configuration structure.
uint32_t clkdiv1
Clock divider bitfield setting, see reference manual for SIM_CLKDIV1.
ADC_Type * dev
ADC device.
use alternate function 2
#define UART_MODE_8N1
8 data bits, no parity, 1 stop bit
Clock configuration for Kinetis CPUs.
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI module configuration options.
CPU specific ADC configuration.
cc2538_ssi_t * dev
SSI device.