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boards/frdm-k64f/include/periph_conf.h
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1 /*
2  * Copyright (C) 2014 Freie Universit├Ąt Berlin
3  * Copyright (C) 2015 PHYTEC Messtechnik GmbH
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser General
6  * Public License v2.1. See the file LICENSE in the top level directory for more
7  * details.
8  */
9 
20 #ifndef PERIPH_CONF_H
21 #define PERIPH_CONF_H
22 
23 #include "periph_cpu.h"
24 
25 #ifdef __cplusplus
26 extern "C"
27 {
28 #endif
29 
34 #define KINETIS_CPU_USE_MCG 1
35 
36 #define KINETIS_MCG_USE_ERC 1
37 #define KINETIS_MCG_USE_PLL 1
38 #define KINETIS_MCG_DCO_RANGE (24000000U)
39 #define KINETIS_MCG_ERC_OSCILLATOR 0
40 #define KINETIS_MCG_ERC_FRDIV 6 /* ERC devider = 1280 */
41 #define KINETIS_MCG_ERC_RANGE 2
42 #define KINETIS_MCG_ERC_FREQ 50000000
43 #define KINETIS_MCG_PLL_PRDIV 19 /* divide factor = 20 */
44 #define KINETIS_MCG_PLL_VDIV0 0 /* multiply factor = 24 */
45 #define KINETIS_MCG_PLL_FREQ 60000000
46 
47 #define CLOCK_CORECLOCK KINETIS_MCG_PLL_FREQ
48 #define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 2)
49 
55 #define PIT_NUMOF (2U)
56 #define PIT_CONFIG { \
57  { \
58  .prescaler_ch = 0, \
59  .count_ch = 1, \
60  }, \
61  { \
62  .prescaler_ch = 2, \
63  .count_ch = 3, \
64  }, \
65  }
66 #define LPTMR_NUMOF (0U)
67 #define LPTMR_CONFIG {}
68 #define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
69 
70 #define PIT_BASECLOCK (CLOCK_BUSCLOCK)
71 #define PIT_CLOCKGATE (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_PIT_SHIFT))
72 #define PIT_ISR_0 isr_pit1
73 #define PIT_ISR_1 isr_pit3
74 #define LPTMR_ISR_0 isr_lptmr0
75 
82 #define UART_NUMOF (1U)
83 #define UART_0_EN 1
84 #define UART_IRQ_PRIO 1
85 #define UART_CLK CLOCK_CORECLOCK
86 
87 /* UART 0 device configuration */
88 #define KINETIS_UART UART_Type
89 #define UART_0_DEV UART0
90 #define UART_0_CLKEN() (SIM->SCGC4 |= (SIM_SCGC4_UART0_MASK))
91 #define UART_0_CLK UART_CLK
92 #define UART_0_IRQ_CHAN UART0_RX_TX_IRQn
93 #define UART_0_ISR isr_uart0_rx_tx
94 /* UART 0 pin configuration */
95 #define UART_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTB_MASK))
96 #define UART_0_PORT PORTB
97 #define UART_0_RX_PIN 16
98 #define UART_0_TX_PIN 17
99 #define UART_0_AF 3
100 
106 static const adc_conf_t adc_config[] = {
107  /* dev, pin, channel */
108  { ADC0, GPIO_PIN(PORT_B, 10), 14 },
109  { ADC0, GPIO_PIN(PORT_B, 11), 15 },
110  { ADC0, GPIO_PIN(PORT_C, 11), 7 },
111  { ADC0, GPIO_PIN(PORT_C, 10), 6 },
112  { ADC0, GPIO_PIN(PORT_C, 8), 4 },
113  { ADC0, GPIO_PIN(PORT_C, 9), 5 },
114 };
115 
116 #define ADC_NUMOF (sizeof(adc_config) / sizeof(adc_config[0]))
117 
123 #define DAC_CONFIG {}
124 #define DAC_NUMOF 0
125 
131 static const pwm_conf_t pwm_config[] = {
132  {
133  .ftm = FTM0,
134  .chan = {
135  { .pin = GPIO_PIN(PORT_A, 4), .af = 3, .ftm_chan = 6 },
136  { .pin = GPIO_PIN(PORT_A, 2), .af = 3, .ftm_chan = 7 },
137  { .pin = GPIO_PIN(PORT_C, 2), .af = 4, .ftm_chan = 1 },
138  { .pin = GPIO_PIN(PORT_C, 3), .af = 4, .ftm_chan = 2 }
139  },
140  .chan_numof = 4,
141  .ftm_num = 0
142  }
143 };
144 
145 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
146 
159 static const uint32_t spi_clk_config[] = {
160  (
161  SPI_CTAR_PBR(2) | SPI_CTAR_BR(6) | /* -> 93750Hz */
162  SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(5) |
163  SPI_CTAR_PASC(2) | SPI_CTAR_ASC(5) |
164  SPI_CTAR_PDT(2) | SPI_CTAR_DT(5)
165  ),
166  (
167  SPI_CTAR_PBR(2) | SPI_CTAR_BR(4) | /* -> 375000Hz */
168  SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(3) |
169  SPI_CTAR_PASC(2) | SPI_CTAR_ASC(3) |
170  SPI_CTAR_PDT(2) | SPI_CTAR_DT(3)
171  ),
172  (
173  SPI_CTAR_PBR(2) | SPI_CTAR_BR(2) | /* -> 1000000Hz */
174  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(4) |
175  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(4) |
176  SPI_CTAR_PDT(0) | SPI_CTAR_DT(4)
177  ),
178  (
179  SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 5000000Hz */
180  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
181  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
182  SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
183  ),
184  (
185  SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | /* -> 7500000Hz */
186  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(1) |
187  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(1) |
188  SPI_CTAR_PDT(0) | SPI_CTAR_DT(1)
189  )
190 };
191 
192 static const spi_conf_t spi_config[] = {
193  {
194  .dev = SPI0,
195  .pin_miso = GPIO_PIN(PORT_D, 3),
196  .pin_mosi = GPIO_PIN(PORT_D, 2),
197  .pin_clk = GPIO_PIN(PORT_D, 1),
198  .pin_cs = {
199  GPIO_PIN(PORT_D, 0),
200  GPIO_UNDEF,
201  GPIO_UNDEF,
202  GPIO_UNDEF,
203  GPIO_UNDEF
204  },
205  .pcr = GPIO_AF_2,
206  .simmask = SIM_SCGC6_SPI0_MASK
207  }
208 };
209 
210 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
211 
218 #define I2C_NUMOF (1U)
219 #define I2C_CLK CLOCK_CORECLOCK
220 #define I2C_0_EN 1
221 #define I2C_IRQ_PRIO 1
222 /* Low (10 kHz): MUL = 4, SCL divider = 2560, total: 10240 */
223 #define KINETIS_I2C_F_ICR_LOW (0x3D)
224 #define KINETIS_I2C_F_MULT_LOW (2)
225 /* Normal (100 kHz): MUL = 2, SCL divider = 240, total: 480 */
226 #define KINETIS_I2C_F_ICR_NORMAL (0x1F)
227 #define KINETIS_I2C_F_MULT_NORMAL (1)
228 /* Fast (400 kHz): MUL = 1, SCL divider = 128, total: 128 */
229 #define KINETIS_I2C_F_ICR_FAST (0x17)
230 #define KINETIS_I2C_F_MULT_FAST (0)
231 /* Fast plus (1000 kHz): MUL = 1, SCL divider = 48, total: 48 */
232 #define KINETIS_I2C_F_ICR_FAST_PLUS (0x10)
233 #define KINETIS_I2C_F_MULT_FAST_PLUS (0)
234 
235 /* I2C 0 device configuration */
236 #define I2C_0_DEV I2C0
237 #define I2C_0_CLKEN() (SIM->SCGC4 |= (SIM_SCGC4_I2C0_MASK))
238 #define I2C_0_CLKDIS() (SIM->SCGC4 &= ~(SIM_SCGC4_I2C0_MASK))
239 #define I2C_0_IRQ I2C0_IRQn
240 #define I2C_0_IRQ_HANDLER isr_i2c0
241 /* I2C 0 pin configuration */
242 #define I2C_0_PORT PORTE
243 #define I2C_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
244 #define I2C_0_PIN_AF 5
245 #define I2C_0_SDA_PIN 25
246 #define I2C_0_SCL_PIN 24
247 #define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
248 
254 #define GPIO_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
255 
261 #define RTT_NUMOF (1U)
262 #define RTC_NUMOF (1U)
263 #define RTT_DEV RTC
264 #define RTT_IRQ RTC_IRQn
265 #define RTT_IRQ_PRIO 10
266 #define RTT_UNLOCK() (SIM->SCGC6 |= (SIM_SCGC6_RTC_MASK))
267 #define RTT_ISR isr_rtc
268 #define RTT_FREQUENCY (1)
269 #define RTT_MAX_VALUE (0xffffffff)
270 
276 #define KINETIS_RNGA RNG
277 #define HWRNG_CLKEN() (SIM->SCGC6 |= (1 << 9))
278 #define HWRNG_CLKDIS() (SIM->SCGC6 &= ~(1 << 9))
279 
281 #ifdef __cplusplus
282 }
283 #endif
284 
285 #endif /* PERIPH_CONF_H */
286 
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
PWM configuration structure.
use alternate function 2
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
CPU specific ADC configuration.
cc2538_ssi_t * dev
SSI device.