boards/frdm-k64f/include/periph_conf.h
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1 /*
2  * Copyright (C) 2014 Freie Universit├Ąt Berlin
3  * Copyright (C) 2015 PHYTEC Messtechnik GmbH
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser General
6  * Public License v2.1. See the file LICENSE in the top level directory for more
7  * details.
8  */
9 
20 #ifndef PERIPH_CONF_H
21 #define PERIPH_CONF_H
22 
23 #include "periph_cpu.h"
24 
25 #ifdef __cplusplus
26 extern "C"
27 {
28 #endif
29 
34 static const clock_config_t clock_config = {
35  /*
36  * This configuration results in the system running from the PLL output with
37  * the following clock frequencies:
38  * Core: 60 MHz
39  * Bus: 60 MHz
40  * Flex: 20 MHz
41  * Flash: 20 MHz
42  */
43  .clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) |
44  SIM_CLKDIV1_OUTDIV3(2) | SIM_CLKDIV1_OUTDIV4(2),
45  .rtc_clc = 0, /* External load caps on board */
46  .osc32ksel = SIM_SOPT1_OSC32KSEL(2),
47  .clock_flags =
48  /* No OSC0_EN, use EXTAL directly without OSC0 */
51  0,
52  .default_mode = KINETIS_MCG_MODE_PEE,
53  /* The board has an external RMII (Ethernet) clock which drives the ERC at 50 MHz */
55  .osc_clc = 0, /* External load caps on board */
56  .oscsel = MCG_C7_OSCSEL(0), /* Use EXTAL for external clock */
57  .fcrdiv = MCG_SC_FCRDIV(0), /* Fast IRC divide by 1 => 4 MHz */
58  .fll_frdiv = MCG_C1_FRDIV(0b111), /* Divide by 1536 => FLL input 32252 Hz */
59  .fll_factor_fei = KINETIS_MCG_FLL_FACTOR_1464, /* FLL freq = 48 MHz */
60  .fll_factor_fee = KINETIS_MCG_FLL_FACTOR_1920, /* FLL freq = 62.5 MHz */
61  .pll_prdiv = MCG_C5_PRDIV0(0b10011), /* Divide by 20 */
62  .pll_vdiv = MCG_C6_VDIV0(0b00000), /* Multiply by 24 => PLL freq = 60 MHz */
63 };
64 #define CLOCK_CORECLOCK (60000000ul)
65 #define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 1)
66 
72 #define PIT_NUMOF (2U)
73 #define PIT_CONFIG { \
74  { \
75  .prescaler_ch = 0, \
76  .count_ch = 1, \
77  }, \
78  { \
79  .prescaler_ch = 2, \
80  .count_ch = 3, \
81  }, \
82  }
83 #define LPTMR_NUMOF (0U)
84 #define LPTMR_CONFIG {}
85 #define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
86 
87 #define PIT_BASECLOCK (CLOCK_BUSCLOCK)
88 #define PIT_ISR_0 isr_pit1
89 #define PIT_ISR_1 isr_pit3
90 #define LPTMR_ISR_0 isr_lptmr0
91 
97 static const uart_conf_t uart_config[] = {
98  {
99  .dev = UART0,
100  .freq = CLOCK_CORECLOCK,
101  .pin_rx = GPIO_PIN(PORT_B, 16),
102  .pin_tx = GPIO_PIN(PORT_B, 17),
103  .pcr_rx = PORT_PCR_MUX(3),
104  .pcr_tx = PORT_PCR_MUX(3),
105  .irqn = UART0_RX_TX_IRQn,
106  .scgc_addr = &SIM->SCGC4,
107  .scgc_bit = SIM_SCGC4_UART0_SHIFT,
108  .mode = UART_MODE_8N1,
109  .type = KINETIS_UART,
110  },
111 };
112 
113 #define UART_0_ISR (isr_uart0_rx_tx)
114 
115 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
116 
122 static const adc_conf_t adc_config[] = {
123  { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 10), .chan = 14 },
124  { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 11), .chan = 15 },
125  { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 11), .chan = 7 },
126  { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 10), .chan = 6 },
127  { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 8), .chan = 4 },
128  { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 9), .chan = 5 }
129 };
130 
131 #define ADC_NUMOF (sizeof(adc_config) / sizeof(adc_config[0]))
132 /*
133  * K64F ADC reference settings:
134  * 0: VREFH/VREFL external pin pair
135  * 1: VREF_OUT internal 1.2 V reference (VREF module must be enabled)
136  * 2-3: reserved
137  */
138 #define ADC_REF_SETTING 0
139 
145 static const pwm_conf_t pwm_config[] = {
146  {
147  .ftm = FTM0,
148  .chan = {
149  { .pin = GPIO_PIN(PORT_A, 4), .af = 3, .ftm_chan = 6 },
150  { .pin = GPIO_PIN(PORT_A, 2), .af = 3, .ftm_chan = 7 },
151  { .pin = GPIO_PIN(PORT_C, 2), .af = 4, .ftm_chan = 1 },
152  { .pin = GPIO_PIN(PORT_C, 3), .af = 4, .ftm_chan = 2 }
153  },
154  .chan_numof = 4,
155  .ftm_num = 0
156  }
157 };
158 
159 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
160 
173 static const uint32_t spi_clk_config[] = {
174  (
175  SPI_CTAR_PBR(2) | SPI_CTAR_BR(6) | /* -> 93750Hz */
176  SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(5) |
177  SPI_CTAR_PASC(2) | SPI_CTAR_ASC(5) |
178  SPI_CTAR_PDT(2) | SPI_CTAR_DT(5)
179  ),
180  (
181  SPI_CTAR_PBR(2) | SPI_CTAR_BR(4) | /* -> 375000Hz */
182  SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(3) |
183  SPI_CTAR_PASC(2) | SPI_CTAR_ASC(3) |
184  SPI_CTAR_PDT(2) | SPI_CTAR_DT(3)
185  ),
186  (
187  SPI_CTAR_PBR(2) | SPI_CTAR_BR(2) | /* -> 1000000Hz */
188  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(4) |
189  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(4) |
190  SPI_CTAR_PDT(0) | SPI_CTAR_DT(4)
191  ),
192  (
193  SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 5000000Hz */
194  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
195  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
196  SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
197  ),
198  (
199  SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | /* -> 7500000Hz */
200  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(1) |
201  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(1) |
202  SPI_CTAR_PDT(0) | SPI_CTAR_DT(1)
203  )
204 };
205 
206 static const spi_conf_t spi_config[] = {
207  {
208  .dev = SPI0,
209  .pin_miso = GPIO_PIN(PORT_D, 3),
210  .pin_mosi = GPIO_PIN(PORT_D, 2),
211  .pin_clk = GPIO_PIN(PORT_D, 1),
212  .pin_cs = {
213  GPIO_PIN(PORT_D, 0),
214  GPIO_UNDEF,
215  GPIO_UNDEF,
216  GPIO_UNDEF,
217  GPIO_UNDEF
218  },
219  .pcr = GPIO_AF_2,
220  .simmask = SIM_SCGC6_SPI0_MASK
221  }
222 };
223 
224 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
225 
232 #define I2C_NUMOF (1U)
233 #define I2C_0_EN 1
234 /* Low (10 kHz): MUL = 4, SCL divider = 1536, total: 6144 */
235 #define KINETIS_I2C_F_ICR_LOW (0x36)
236 #define KINETIS_I2C_F_MULT_LOW (2)
237 /* Normal (100 kHz): MUL = 2, SCL divider = 320, total: 640 */
238 #define KINETIS_I2C_F_ICR_NORMAL (0x25)
239 #define KINETIS_I2C_F_MULT_NORMAL (1)
240 /* Fast (400 kHz): MUL = 1, SCL divider = 160, total: 160 */
241 #define KINETIS_I2C_F_ICR_FAST (0x1D)
242 #define KINETIS_I2C_F_MULT_FAST (0)
243 /* Fast plus (1000 kHz): MUL = 1, SCL divider = 64, total: 64 */
244 #define KINETIS_I2C_F_ICR_FAST_PLUS (0x12)
245 #define KINETIS_I2C_F_MULT_FAST_PLUS (0)
246 
247 /* I2C 0 device configuration */
248 #define I2C_0_DEV I2C0
249 #define I2C_0_CLKEN() (SIM->SCGC4 |= (SIM_SCGC4_I2C0_MASK))
250 #define I2C_0_CLKDIS() (SIM->SCGC4 &= ~(SIM_SCGC4_I2C0_MASK))
251 #define I2C_0_IRQ I2C0_IRQn
252 #define I2C_0_IRQ_HANDLER isr_i2c0
253 /* I2C 0 pin configuration */
254 #define I2C_0_PORT PORTE
255 #define I2C_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
256 #define I2C_0_PIN_AF 5
257 #define I2C_0_SDA_PIN 25
258 #define I2C_0_SCL_PIN 24
259 #define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
260 
262 #ifdef __cplusplus
263 }
264 #endif
265 
266 #endif /* PERIPH_CONF_H */
267 
cc2538_uart_t * dev
pointer to the used UART device
PLL Engaged External Mode.
PWM device configuration.
uint32_t clkdiv1
Clock divider bitfield setting.
pwm_conf_chan_t chan[3]
channel configuration
8 data bits, no parity, 1 stop bit
ADC_TypeDef * dev
ADC device used.
use alternate function 2
Clock configuration for Kinetis CPUs.
UART device configuration.
SPI module configuration options.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
#define CLOCK_CORECLOCK
Core clock frequency, used by the ARM core and certain hardware modules in Kinetis CPUs...
Definition: mcg.h:137
ADC device configuration.
Use the fast internal reference clock as MCGIRCLK signal.
Kinetis UART module type.
cc2538_ssi_t * dev
SSI device.