boards/fox/include/periph_conf.h
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1 /*
2  * Copyright (C) 2014 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 /* high speed clock configuration:
33  * 0 := use internal HSI oscillator (always 8MHz)
34  * HSE frequency value := use external HSE oscillator with given freq [in Hz]
35  * must be 4000000 <= value <= 16000000 */
36 #define CLOCK_HSE (16000000U)
37 /* low speed clock configuration:
38  * 0 := use internal LSI oscillator (~40kHz)
39  * 1 := use extern LSE oscillator, always 32.768kHz */
40 #define CLOCK_LSE (1)
41 /* targeted system clock speed [in Hz], must be <= 72MHz */
42 #define CLOCK_CORECLOCK (72000000U)
43 /* PLL configuration, set both values to zero to disable PLL usage. The values
44  * must be set to satisfy the following equation:
45  * CORECLOCK := CLOCK_SOURCE / PLL_DIV * PLL_MUL
46  * with
47  * 1 <= CLOCK_PLL_DIV <= 2
48  * 2 <= CLOCK_PLL_MUL <= 17 */
49 #define CLOCK_PLL_DIV (2)
50 #define CLOCK_PLL_MUL (9)
51 /* AHB and APBx bus clock configuration, keep in mind the following constraints:
52  * ABP1 <= 36MHz
53  */
54 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
55 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
56 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
57 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
58 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
59 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
60 
66 #define ADC_NUMOF (0)
67 
73 #define DAC_NUMOF (0)
74 
80 static const timer_conf_t timer_config[] = {
81  {
82  .dev = TIM2,
83  .max = 0x0000ffff,
84  .rcc_mask = RCC_APB1ENR_TIM2EN,
85  .bus = APB1,
86  .irqn = TIM2_IRQn
87  },
88  {
89  .dev = TIM3,
90  .max = 0x0000ffff,
91  .rcc_mask = RCC_APB1ENR_TIM3EN,
92  .bus = APB1,
93  .irqn = TIM3_IRQn
94  }
95 };
96 
97 #define TIMER_0_ISR isr_tim2
98 #define TIMER_1_ISR isr_tim3
99 
100 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
101 
107 static const uart_conf_t uart_config[] = {
108  {
109  .dev = USART2,
110  .rcc_mask = RCC_APB1ENR_USART2EN,
111  .rx_pin = GPIO_PIN(PORT_A, 3),
112  .tx_pin = GPIO_PIN(PORT_A, 2),
113  .bus = APB1,
114  .irqn = USART2_IRQn
115  },
116  {
117  .dev = USART1,
118  .rcc_mask = RCC_APB2ENR_USART1EN,
119  .rx_pin = GPIO_PIN(PORT_A, 10),
120  .tx_pin = GPIO_PIN(PORT_A, 9),
121  .bus = APB2,
122  .irqn = USART1_IRQn
123  }
124 };
125 
126 #define UART_0_ISR (isr_usart2)
127 #define UART_1_ISR (isr_usart1)
128 
129 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
130 
139 static const uint8_t spi_divtable[2][5] = {
140  { /* for APB1 @ 36000000Hz */
141  7, /* -> 140625Hz */
142  6, /* -> 281250Hz */
143  4, /* -> 1125000Hz */
144  2, /* -> 4500000Hz */
145  1 /* -> 9000000Hz */
146  },
147  { /* for APB2 @ 72000000Hz */
148  7, /* -> 281250Hz */
149  7, /* -> 281250Hz */
150  5, /* -> 1125000Hz */
151  3, /* -> 4500000Hz */
152  2 /* -> 9000000Hz */
153  }
154 };
155 
156 static const spi_conf_t spi_config[] = {
157  {
158  .dev = SPI2,
159  .mosi_pin = GPIO_PIN(PORT_B, 15),
160  .miso_pin = GPIO_PIN(PORT_B, 14),
161  .sclk_pin = GPIO_PIN(PORT_B, 13),
162  .cs_pin = GPIO_UNDEF,
163  .rccmask = RCC_APB1ENR_SPI2EN,
164  .apbbus = APB1
165  }
166 };
167 
168 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
169 
175 #define RTT_NUMOF (1U)
176 #define RTT_IRQ_PRIO 1
177 
178 #define RTT_DEV RTC
179 #define RTT_IRQ RTC_IRQn
180 #define RTT_ISR isr_rtc
181 #define RTT_MAX_VALUE (0xffffffff)
182 #define RTT_FREQUENCY (1) /* in Hz */
183 #define RTT_PRESCALER (0x7fff) /* run with 1 Hz */
184 
190 #define I2C_NUMOF (1U)
191 #define I2C_0_EN 1
192 #define I2C_IRQ_PRIO 1
193 #define I2C_APBCLK (CLOCK_APB1)
194 
195 /* I2C 0 device configuration */
196 #define I2C_0_DEV I2C1
197 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
198 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
199 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
200 #define I2C_0_EVT_ISR isr_i2c1_ev
201 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
202 #define I2C_0_ERR_ISR isr_i2c1_er
203 /* I2C 0 pin configuration */
204 #define I2C_0_SCL_PIN GPIO_PIN(PORT_B,6)
205 #define I2C_0_SDA_PIN GPIO_PIN(PORT_B,7)
206 
208 #ifdef __cplusplus
209 }
210 #endif
211 
212 #endif /* PERIPH_CONF_H */
213 
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
cc2538_ssi_t * dev
SSI device.