cpu.h
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1 /*
2  * Copyright (C) 2015 Kaspar Schleiser <kaspar@schleiser.de>
3  * 2014 Freie Universit├Ąt Berlin, Hinnerk van Bruinehsen
4  * 2018 RWTH Aachen, Josua Arndt <jarndt@ias.rwth-aachen.de>
5  *
6  * This file is subject to the terms and conditions of the GNU Lesser
7  * General Public License v2.1. See the file LICENSE in the top level
8  * directory for more details.
9  */
10 
30 #ifndef CPU_H
31 #define CPU_H
32 
33 #include <stdio.h>
34 #include <stdint.h>
35 
36 #include <avr/interrupt.h>
37 #include "cpu_conf.h"
38 #include "sched.h"
39 #include "thread.h"
40 
41 #ifdef __cplusplus
42 extern "C"
43 {
44 #endif
45 
50 #define PERIPH_I2C_NEED_READ_REG
51 #define PERIPH_I2C_NEED_WRITE_REG
52 #define PERIPH_I2C_NEED_READ_REGS
53 #define PERIPH_I2C_NEED_WRITE_REGS
54 
60 #define ATMEGA_STATE_FLAG_ISR (0x80U)
61 #define ATMEGA_STATE_FLAG_UART0_TX (0x01U)
62 #define ATMEGA_STATE_FLAG_UART1_TX (0x02U)
63 #define ATMEGA_STATE_FLAG_UART_TX(x) (0x01U << x)
88 extern uint8_t atmega_state;
89 
103 static inline uint8_t atmega_get_state(void)
104 {
105  uint8_t state;
106  __asm__ volatile(
107  "lds %[state], atmega_state \n\t"
108  : [state] "=r" (state)
109  :
110  : "memory"
111 
112  );
113 
114  return state;
115 }
116 
120 static inline void atmega_enter_isr(void)
121 {
122  /* This flag is only called from IRQ context, and nested IRQs are not
123  * supported as of now. The flag will be unset before the IRQ context is
124  * left, so no need to use memory barriers or atomics here
125  */
127 }
128 
135 static inline int atmega_is_uart_tx_pending(void)
136 {
137  uint8_t state = atmega_get_state();
139 }
140 
144 void atmega_exit_isr(void);
145 
149 void cpu_init(void);
150 
154 static inline void __attribute__((always_inline)) cpu_print_last_instruction(void)
155 {
156  uint8_t hi;
157  uint8_t lo;
158  uint16_t ptr;
159 
160  __asm__ volatile ("in __tmp_reg__, __SP_H__ \n\t"
161  "mov %0, __tmp_reg__ \n\t"
162  : "=g" (hi));
163 
164  __asm__ volatile ("in __tmp_reg__, __SP_L__ \n\t"
165  "mov %0, __tmp_reg__ \n\t"
166  : "=g" (lo));
167  ptr = hi << 8 | lo;
168  printf("Stack Pointer: 0x%04x\n", ptr);
169 }
170 
176 enum {
177  CPU_ATMEGA_CLK_SCALE_DIV1 = 0,
178  CPU_ATMEGA_CLK_SCALE_DIV2 = 1,
179  CPU_ATMEGA_CLK_SCALE_DIV4 = 2,
180  CPU_ATMEGA_CLK_SCALE_DIV8 = 3,
181  CPU_ATMEGA_CLK_SCALE_DIV16 = 4,
182  CPU_ATMEGA_CLK_SCALE_DIV32 = 5,
183  CPU_ATMEGA_CLK_SCALE_DIV64 = 6,
184  CPU_ATMEGA_CLK_SCALE_DIV128 = 7,
185  CPU_ATMEGA_CLK_SCALE_DIV256 = 8,
186  CPU_ATMEGA_CLK_SCALE_DIV512 = 9,
187 };
188 
192 static inline void atmega_set_prescaler(uint8_t clk_scale)
193 {
194  /* Enable clock change */
195  /* Must be assignment to set all other bits to zero, see datasheet */
196  CLKPR = (1 << CLKPCE);
197 
198  /* Write clock within 4 cycles */
199  CLKPR = clk_scale;
200 }
201 
205 void atmega_stdio_init(void);
206 
207 #ifdef __cplusplus
208 }
209 #endif
210 
211 #endif /* CPU_H */
212 
static uint8_t atmega_get_state(void)
Atomically read the state (atmega_state)
Definition: cpu.h:103
static void atmega_set_prescaler(uint8_t clk_scale)
Initializes system clock prescaler.
Definition: cpu.h:192
void cpu_init(void)
Initialization of the CPU.
void atmega_stdio_init(void)
Initializes avrlibc stdio.
Implementation specific CPU configuration options.
#define ATMEGA_STATE_FLAG_UART0_TX
TX pending for UART 0.
Definition: cpu.h:61
static void atmega_enter_isr(void)
Run this code on entering interrupt routines.
Definition: cpu.h:120
Scheduler API definition.
#define ATMEGA_STATE_FLAG_ISR
In ISR.
Definition: cpu.h:60
uint8_t atmega_state
Global variable containing the current state of the MCU.
stdio.h wrapper for MSP430
void atmega_exit_isr(void)
Run this code on exiting interrupt routines.
static void cpu_print_last_instruction(void)
Print the last instruction&#39;s address.
Definition: cpu.h:154
#define ATMEGA_STATE_FLAG_UART1_TX
TX pending for UART 1.
Definition: cpu.h:62
static int atmega_is_uart_tx_pending(void)
Check if TX on any present UART device is still pending.
Definition: cpu.h:135