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at86rf2xx_registers.h
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1/*
2 * Copyright (C) 2013 Alaeddine Weslati <alaeddine.weslati@inria.fr>
3 * Copyright (C) 2015 Freie Universität Berlin
4 *
5 * This file is subject to the terms and conditions of the GNU Lesser
6 * General Public License v2.1. See the file LICENSE in the top level
7 * directory for more details.
8 */
9
24#ifndef AT86RF2XX_REGISTERS_H
25#define AT86RF2XX_REGISTERS_H
26
27#include "at86rf2xx.h"
28
29#ifdef __cplusplus
30extern "C" {
31#endif
32
37#define AT86RF212B_PARTNUM (0x07)
38#define AT86RF231_PARTNUM (0x03)
39#define AT86RF232_PARTNUM (0x0a)
40#define AT86RF233_PARTNUM (0x0b)
41#define AT86RFA1_PARTNUM (0x83)
42#define AT86RFR2_PARTNUM (0x94)
49#ifdef MODULE_AT86RF212B
50#define AT86RF2XX_PARTNUM AT86RF212B_PARTNUM
51#elif MODULE_AT86RF232
52#define AT86RF2XX_PARTNUM AT86RF232_PARTNUM
53#elif MODULE_AT86RF233
54#define AT86RF2XX_PARTNUM AT86RF233_PARTNUM
55#elif MODULE_AT86RFA1
56#define AT86RF2XX_PARTNUM AT86RFA1_PARTNUM
57#elif MODULE_AT86RFR2
58#define AT86RF2XX_PARTNUM AT86RFR2_PARTNUM
59#else /* MODULE_AT86RF231 as default device */
60#define AT86RF2XX_PARTNUM AT86RF231_PARTNUM
61#endif
64/*
65 * memory-mapped transceiver
66 */
67#if defined(MODULE_AT86RFA1) || defined(MODULE_AT86RFR2)
68
69#include <avr/io.h>
70
75#define AT86RF2XX_REG__TRX_STATUS (&TRX_STATUS)
76#define AT86RF2XX_REG__TRX_STATE (&TRX_STATE)
77#define AT86RF2XX_REG__TRX_CTRL_0 (&TRX_CTRL_0)
78#define AT86RF2XX_REG__TRX_CTRL_1 (&TRX_CTRL_1)
79#define AT86RF2XX_REG__PHY_TX_PWR (&PHY_TX_PWR)
80#define AT86RF2XX_REG__PHY_RSSI (&PHY_RSSI)
81#define AT86RF2XX_REG__PHY_ED_LEVEL (&PHY_ED_LEVEL)
82#define AT86RF2XX_REG__PHY_CC_CCA (&PHY_CC_CCA)
83#define AT86RF2XX_REG__CCA_THRES (&CCA_THRES)
84#define AT86RF2XX_REG__RX_CTRL (&RX_CTRL)
85#define AT86RF2XX_REG__SFD_VALUE (&SFD_VALUE)
86#define AT86RF2XX_REG__TRX_CTRL_2 (&TRX_CTRL_2)
87#define AT86RF2XX_REG__TRX_RPC (&TRX_RPC)
88#define AT86RF2XX_REG__ANT_DIV (&ANT_DIV)
89#define AT86RF2XX_REG__IRQ_MASK (&IRQ_MASK)
90#ifdef IRQ_MASK1
91#define AT86RF2XX_REG__IRQ_MASK1 (&IRQ_MASK1)
92#endif
93#define AT86RF2XX_REG__IRQ_STATUS (&IRQ_STATUS)
94#define AT86RF2XX_REG__IRQ_STATUS1 (&IRQ_STATUS1)
95#define AT86RF2XX_REG__VREG_CTRL (&VREG_CTRL)
96#define AT86RF2XX_REG__BATMON (&BATMON)
97#define AT86RF2XX_REG__XOSC_CTRL (&XOSC_CTRL)
98#define AT86RF2XX_REG__CC_CTRL_0 (&CC_CTRL_0)
99#define AT86RF2XX_REG__CC_CTRL_1 (&CC_CTRL_1)
100#define AT86RF2XX_REG__RX_SYN (&RX_SYN)
101#define AT86RF2XX_REG__XAH_CTRL_1 (&XAH_CTRL_1)
102#define AT86RF2XX_REG__FTN_CTRL (&FTN_CTRL)
103#define AT86RF2XX_REG__PLL_CF (&PLL_CF)
104#define AT86RF2XX_REG__PLL_DCU (&PLL_DCU)
105#define AT86RF2XX_REG__PART_NUM (&PART_NUM)
106#define AT86RF2XX_REG__VERSION_NUM (&VERSION_NUM)
107#define AT86RF2XX_REG__MAN_ID_0 (&MAN_ID_0)
108#define AT86RF2XX_REG__MAN_ID_1 (&MAN_ID_1)
109#define AT86RF2XX_REG__SHORT_ADDR_0 (&SHORT_ADDR_0)
110#define AT86RF2XX_REG__SHORT_ADDR_1 (&SHORT_ADDR_1)
111#define AT86RF2XX_REG__PAN_ID_0 (&PAN_ID_0)
112#define AT86RF2XX_REG__PAN_ID_1 (&PAN_ID_1)
113#define AT86RF2XX_REG__IEEE_ADDR_0 (&IEEE_ADDR_0)
114#define AT86RF2XX_REG__IEEE_ADDR_1 (&IEEE_ADDR_1)
115#define AT86RF2XX_REG__IEEE_ADDR_2 (&IEEE_ADDR_2)
116#define AT86RF2XX_REG__IEEE_ADDR_3 (&IEEE_ADDR_3)
117#define AT86RF2XX_REG__IEEE_ADDR_4 (&IEEE_ADDR_4)
118#define AT86RF2XX_REG__IEEE_ADDR_5 (&IEEE_ADDR_5)
119#define AT86RF2XX_REG__IEEE_ADDR_6 (&IEEE_ADDR_6)
120#define AT86RF2XX_REG__IEEE_ADDR_7 (&IEEE_ADDR_7)
121#define AT86RF2XX_REG__XAH_CTRL_0 (&XAH_CTRL_0)
122#define AT86RF2XX_REG__CSMA_SEED_0 (&CSMA_SEED_0)
123#define AT86RF2XX_REG__CSMA_SEED_1 (&CSMA_SEED_1)
124#define AT86RF2XX_REG__CSMA_BE (&CSMA_BE)
125#define AT86RF2XX_REG__TST_CTRL_DIGI (&TST_CTRL_DIGI)
126#define AT86RF2XX_REG__TRXFBST (&TRXFBST)
127#define AT86RF2XX_REG__TRXFBEND (&TRXFBEND)
128#define AT86RF2XX_REG__TRXPR (&TRXPR)
135#define AT86RF2XX_TRX_CTRL_0_MASK__PMU_EN (0x40)
136#define AT86RF2XX_TRX_CTRL_0_MASK__PMU_START (0x20)
137#define AT86RF2XX_TRX_CTRL_0_MASK__PMU_IF_INV (0x10)
144#define AT86RF2XX_TRX_CTRL_1_MASK__PA_EXT_EN (0x80)
145#define AT86RF2XX_TRX_CTRL_1_MASK__IRQ_2_EXT_EN (0x40)
146#define AT86RF2XX_TRX_CTRL_1_MASK__TX_AUTO_CRC_ON (0x20)
147#define AT86RF2XX_TRX_CTRL_1_MASK__PLL_TX_FLT (0x10)
154#define AT86RF2XX_TRX_CTRL_2_MASK__RX_SAFE_MODE (0x80)
155#define AT86RF2XX_TRX_CTRL_2_MASK__OQPSK_DATA_RATE (0x03)
162#define AT86RF2XX_IRQ_STATUS_MASK__AWAKE (0x80)
163#define AT86RF2XX_IRQ_STATUS_MASK__TX_END (0x40)
164#define AT86RF2XX_IRQ_STATUS_MASK__AMI (0x20)
165#define AT86RF2XX_IRQ_STATUS_MASK__CCA_ED_DONE (0x10)
166#define AT86RF2XX_IRQ_STATUS_MASK__RX_END (0x08)
167#define AT86RF2XX_IRQ_STATUS_MASK__RX_START (0x04)
168#define AT86RF2XX_IRQ_STATUS_MASK__PLL_UNLOCK (0x02)
169#define AT86RF2XX_IRQ_STATUS_MASK__PLL_LOCK (0x01)
170
171/* Map TX_END and RX_END to TRX_END to be compatible to SPI Devices */
172#define AT86RF2XX_IRQ_STATUS_MASK__TRX_END (0x48)
179#define AT86RF2XX_IRQ_STATUS_MASK1__TX_START (0x01)
180#define AT86RF2XX_IRQ_STATUS_MASK1__MAF_0_AMI (0x02)
181#define AT86RF2XX_IRQ_STATUS_MASK1__MAF_1_AMI (0x04)
182#define AT86RF2XX_IRQ_STATUS_MASK1__MAF_2_AMI (0x08)
183#define AT86RF2XX_IRQ_STATUS_MASK1__MAF_3_AMI (0x10)
186#else
187/*
188 * SPI based transceiver
189 */
190
195#define AT86RF2XX_ACCESS_REG (0x80)
196#define AT86RF2XX_ACCESS_FB (0x20)
197#define AT86RF2XX_ACCESS_SRAM (0x00)
198#define AT86RF2XX_ACCESS_READ (0x00)
199#define AT86RF2XX_ACCESS_WRITE (0x40)
206#define AT86RF2XX_REG__TRX_STATUS (0x01)
207#define AT86RF2XX_REG__TRX_STATE (0x02)
208#define AT86RF2XX_REG__TRX_CTRL_0 (0x03)
209#define AT86RF2XX_REG__TRX_CTRL_1 (0x04)
210#define AT86RF2XX_REG__PHY_TX_PWR (0x05)
211#define AT86RF2XX_REG__PHY_RSSI (0x06)
212#define AT86RF2XX_REG__PHY_ED_LEVEL (0x07)
213#define AT86RF2XX_REG__PHY_CC_CCA (0x08)
214#define AT86RF2XX_REG__CCA_THRES (0x09)
215#define AT86RF2XX_REG__RX_CTRL (0x0A)
216#define AT86RF2XX_REG__SFD_VALUE (0x0B)
217#define AT86RF2XX_REG__TRX_CTRL_2 (0x0C)
218#define AT86RF2XX_REG__ANT_DIV (0x0D)
219#define AT86RF2XX_REG__IRQ_MASK (0x0E)
220#define AT86RF2XX_REG__IRQ_STATUS (0x0F)
221#define AT86RF2XX_REG__VREG_CTRL (0x10)
222#define AT86RF2XX_REG__BATMON (0x11)
223#define AT86RF2XX_REG__XOSC_CTRL (0x12)
224#define AT86RF2XX_REG__CC_CTRL_1 (0x14)
225#define AT86RF2XX_REG__RX_SYN (0x15)
226#ifdef MODULE_AT86RF212B
227#define AT86RF2XX_REG__RF_CTRL_0 (0x16)
228#elif defined(MODULE_AT86RF233)
229#define AT86RF2XX_REG__TRX_RPC (0x16)
230#endif
231#define AT86RF2XX_REG__XAH_CTRL_1 (0x17)
232#define AT86RF2XX_REG__FTN_CTRL (0x18)
233#if AT86RF2XX_HAVE_RETRIES
234#define AT86RF2XX_REG__XAH_CTRL_2 (0x19)
235#endif
236#define AT86RF2XX_REG__PLL_CF (0x1A)
237#define AT86RF2XX_REG__PLL_DCU (0x1B)
238#define AT86RF2XX_REG__PART_NUM (0x1C)
239#define AT86RF2XX_REG__VERSION_NUM (0x1D)
240#define AT86RF2XX_REG__MAN_ID_0 (0x1E)
241#define AT86RF2XX_REG__MAN_ID_1 (0x1F)
242#define AT86RF2XX_REG__SHORT_ADDR_0 (0x20)
243#define AT86RF2XX_REG__SHORT_ADDR_1 (0x21)
244#define AT86RF2XX_REG__PAN_ID_0 (0x22)
245#define AT86RF2XX_REG__PAN_ID_1 (0x23)
246#define AT86RF2XX_REG__IEEE_ADDR_0 (0x24)
247#define AT86RF2XX_REG__IEEE_ADDR_1 (0x25)
248#define AT86RF2XX_REG__IEEE_ADDR_2 (0x26)
249#define AT86RF2XX_REG__IEEE_ADDR_3 (0x27)
250#define AT86RF2XX_REG__IEEE_ADDR_4 (0x28)
251#define AT86RF2XX_REG__IEEE_ADDR_5 (0x29)
252#define AT86RF2XX_REG__IEEE_ADDR_6 (0x2A)
253#define AT86RF2XX_REG__IEEE_ADDR_7 (0x2B)
254#define AT86RF2XX_REG__XAH_CTRL_0 (0x2C)
255#define AT86RF2XX_REG__CSMA_SEED_0 (0x2D)
256#define AT86RF2XX_REG__CSMA_SEED_1 (0x2E)
257#define AT86RF2XX_REG__CSMA_BE (0x2F)
258#define AT86RF2XX_REG__TST_CTRL_DIGI (0x36)
265#define AT86RF2XX_TRX_CTRL_0_MASK__PAD_IO (0xC0)
266#define AT86RF2XX_TRX_CTRL_0_MASK__PAD_IO_CLKM (0x30)
267#define AT86RF2XX_TRX_CTRL_0_MASK__CLKM_SHA_SEL (0x08)
268#define AT86RF2XX_TRX_CTRL_0_MASK__CLKM_CTRL (0x07)
269
270#define AT86RF2XX_TRX_CTRL_0_DEFAULT__PAD_IO (0x00)
271#define AT86RF2XX_TRX_CTRL_0_DEFAULT__PAD_IO_CLKM (0x10)
272#define AT86RF2XX_TRX_CTRL_0_DEFAULT__CLKM_SHA_SEL (0x08)
273#define AT86RF2XX_TRX_CTRL_0_DEFAULT__CLKM_CTRL (0x01)
274
275#define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__OFF (0x00)
276#define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__1MHz (0x01)
277#define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__2MHz (0x02)
278#define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__4MHz (0x03)
279#define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__8MHz (0x04)
280#define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__16MHz (0x05)
281#define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__250kHz (0x06)
282#define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__62_5kHz (0x07)
289#define AT86RF2XX_TRX_CTRL_1_MASK__PA_EXT_EN (0x80)
290#define AT86RF2XX_TRX_CTRL_1_MASK__IRQ_2_EXT_EN (0x40)
291#define AT86RF2XX_TRX_CTRL_1_MASK__TX_AUTO_CRC_ON (0x20)
292#define AT86RF2XX_TRX_CTRL_1_MASK__RX_BL_CTRL (0x10)
293#define AT86RF2XX_TRX_CTRL_1_MASK__SPI_CMD_MODE (0x0C)
294#define AT86RF2XX_TRX_CTRL_1_MASK__IRQ_MASK_MODE (0x02)
295#define AT86RF2XX_TRX_CTRL_1_MASK__IRQ_POLARITY (0x01)
302#define AT86RF2XX_TRX_CTRL_2_MASK__RX_SAFE_MODE (0x80)
303#define AT86RF2XX_TRX_CTRL_2_MASK__FREQ_MODE (0x3F)
304#define AT86RF2XX_TRX_CTRL_2_MASK__TRX_OFF_AVDD_EN (0x40)
305#define AT86RF2XX_TRX_CTRL_2_MASK__OQPSK_SCRAM_EN (0x20)
306#define AT86RF2XX_TRX_CTRL_2_MASK__ALT_SPECTRUM (0x10)
307#define AT86RF2XX_TRX_CTRL_2_MASK__BPSK_OQPSK (0x08)
308#define AT86RF2XX_TRX_CTRL_2_MASK__SUB_MODE (0x04)
309#define AT86RF2XX_TRX_CTRL_2_MASK__OQPSK_DATA_RATE (0x03)
316#define AT86RF2XX_IRQ_STATUS_MASK__BAT_LOW (0x80)
317#define AT86RF2XX_IRQ_STATUS_MASK__TRX_UR (0x40)
318#define AT86RF2XX_IRQ_STATUS_MASK__AMI (0x20)
319#define AT86RF2XX_IRQ_STATUS_MASK__CCA_ED_DONE (0x10)
320#define AT86RF2XX_IRQ_STATUS_MASK__TRX_END (0x08)
321#define AT86RF2XX_IRQ_STATUS_MASK__RX_START (0x04)
322#define AT86RF2XX_IRQ_STATUS_MASK__PLL_UNLOCK (0x02)
323#define AT86RF2XX_IRQ_STATUS_MASK__PLL_LOCK (0x01)
326#endif /* END external spi transceiver */
331#define AT86RF2XX_TRX_STATUS_MASK__CCA_DONE (0x80)
332#define AT86RF2XX_TRX_STATUS_MASK__CCA_STATUS (0x40)
333#define AT86RF2XX_TRX_STATUS_MASK__TRX_STATUS (0x1F)
334
335#define AT86RF2XX_TRX_STATUS__P_ON (0x00)
336#define AT86RF2XX_TRX_STATUS__BUSY_RX (0x01)
337#define AT86RF2XX_TRX_STATUS__BUSY_TX (0x02)
338#define AT86RF2XX_TRX_STATUS__RX_ON (0x06)
339#define AT86RF2XX_TRX_STATUS__TRX_OFF (0x08)
340#define AT86RF2XX_TRX_STATUS__PLL_ON (0x09)
341#define AT86RF2XX_TRX_STATUS__SLEEP (0x0F)
342#define AT86RF2XX_TRX_STATUS__BUSY_RX_AACK (0x11)
343#define AT86RF2XX_TRX_STATUS__BUSY_TX_ARET (0x12)
344#define AT86RF2XX_TRX_STATUS__RX_AACK_ON (0x16)
345#define AT86RF2XX_TRX_STATUS__TX_ARET_ON (0x19)
346#define AT86RF2XX_TRX_STATUS__RX_ON_NOCLK (0x1C)
347#define AT86RF2XX_TRX_STATUS__RX_AACK_ON_NOCLK (0x1D)
348#define AT86RF2XX_TRX_STATUS__BUSY_RX_AACK_NOCLK (0x1E)
349#define AT86RF2XX_TRX_STATUS__STATE_TRANSITION_IN_PROGRESS (0x1F)
356#define AT86RF2XX_TRX_STATE_MASK__TRAC (0xe0)
357
358#define AT86RF2XX_TRX_STATE__NOP (0x00)
359#define AT86RF2XX_TRX_STATE__TX_START (0x02)
360#define AT86RF2XX_TRX_STATE__FORCE_TRX_OFF (0x03)
361#define AT86RF2XX_TRX_STATE__FORCE_PLL_ON (0x04)
362#define AT86RF2XX_TRX_STATE__RX_ON (0x06)
363#define AT86RF2XX_TRX_STATE__TRX_OFF (0x08)
364#define AT86RF2XX_TRX_STATE__PLL_ON (0x09)
365#define AT86RF2XX_TRX_STATE__RX_AACK_ON (0x16)
366#define AT86RF2XX_TRX_STATE__TX_ARET_ON (0x19)
367#define AT86RF2XX_TRX_STATE__TRAC_SUCCESS (0x00)
368#define AT86RF2XX_TRX_STATE__TRAC_SUCCESS_DATA_PENDING (0x20)
369#define AT86RF2XX_TRX_STATE__TRAC_SUCCESS_WAIT_FOR_ACK (0x40)
370#define AT86RF2XX_TRX_STATE__TRAC_CHANNEL_ACCESS_FAILURE (0x60)
371#define AT86RF2XX_TRX_STATE__TRAC_NO_ACK (0xa0)
372#define AT86RF2XX_TRX_STATE__TRAC_INVALID (0xe0)
379#define AT86RF2XX_PHY_CC_CCA_MASK__CCA_REQUEST (0x80)
380#define AT86RF2XX_PHY_CC_CCA_MASK__CCA_MODE (0x60)
381#define AT86RF2XX_PHY_CC_CCA_MASK__CHANNEL (0x1F)
382
383#define AT86RF2XX_PHY_CC_CCA_DEFAULT__CCA_MODE (0x20)
390#define AT86RF2XX_CCA_THRES_MASK__CCA_ED_THRES (0x0F)
391
392#define AT86RF2XX_CCA_THRES_MASK__RSVD_HI_NIBBLE (0xC0)
399#ifdef MODULE_AT86RF212B
400#define AT86RF2XX_PHY_TX_PWR_MASK__PA_BOOST (0x80)
401#define AT86RF2XX_PHY_TX_PWR_MASK__GC_PA (0x60)
402#define AT86RF2XX_PHY_TX_PWR_MASK__TX_PWR (0x1F)
403#elif MODULE_AT86RF231
404#define AT86RF2XX_PHY_TX_PWR_MASK__PA_BUF_LT (0xC0)
405#define AT86RF2XX_PHY_TX_PWR_MASK__PA_LT (0x30)
406#define AT86RF2XX_PHY_TX_PWR_MASK__TX_PWR (0x0F)
407#else
408#define AT86RF2XX_PHY_TX_PWR_MASK__TX_PWR (0x0F)
409#endif
410#define AT86RF2XX_PHY_TX_PWR_DEFAULT__PA_BUF_LT (0xC0)
411#define AT86RF2XX_PHY_TX_PWR_DEFAULT__PA_LT (0x00)
412#define AT86RF2XX_PHY_TX_PWR_DEFAULT__TX_PWR (0x00)
419#define AT86RF2XX_PHY_RSSI_MASK__RX_CRC_VALID (0x80)
420#define AT86RF2XX_PHY_RSSI_MASK__RND_VALUE (0x60)
421#define AT86RF2XX_PHY_RSSI_MASK__RSSI (0x1F)
428#define AT86RF2XX_XOSC_CTRL__XTAL_MODE_CRYSTAL (0xF0)
429#define AT86RF2XX_XOSC_CTRL__XTAL_MODE_EXTERNAL (0xF0)
436#define AT86RF2XX_RX_SYN__RX_PDT_DIS (0x80)
437#define AT86RF2XX_RX_SYN__RX_OVERRIDE (0x70)
438#define AT86RF2XX_RX_SYN__RX_PDT_LEVEL (0x0F)
445#define AT86RF2XX_TIMING__VCC_TO_P_ON (330)
446#define AT86RF2XX_TIMING__SLEEP_TO_TRX_OFF (380)
447#define AT86RF2XX_TIMING__TRX_OFF_TO_PLL_ON (110)
448#define AT86RF2XX_TIMING__TRX_OFF_TO_RX_ON (110)
449#define AT86RF2XX_TIMING__PLL_ON_TO_BUSY_TX (16)
450#define AT86RF2XX_TIMING__RESET (100)
451#define AT86RF2XX_TIMING__RESET_TO_TRX_OFF (37)
458#define AT86RF2XX_XAH_CTRL_0__MAX_FRAME_RETRIES (0xF0)
459#define AT86RF2XX_XAH_CTRL_0__MAX_CSMA_RETRIES (0x0E)
460#define AT86RF2XX_XAH_CTRL_0__SLOTTED_OPERATION (0x01)
467#define AT86RF2XX_XAH_CTRL_1__AACK_FLTR_RES_FT (0x20)
468#define AT86RF2XX_XAH_CTRL_1__AACK_UPLD_RES_FT (0x10)
469#define AT86RF2XX_XAH_CTRL_1__AACK_ACK_TIME (0x04)
470#define AT86RF2XX_XAH_CTRL_1__AACK_PROM_MODE (0x02)
482#if AT86RF2XX_HAVE_RETRIES
483#define AT86RF2XX_XAH_CTRL_2__ARET_FRAME_RETRIES_MASK (0xF0)
484#define AT86RF2XX_XAH_CTRL_2__ARET_FRAME_RETRIES_OFFSET (4)
485#define AT86RF2XX_XAH_CTRL_2__ARET_CSMA_RETRIES_MASK (0x0E)
486#define AT86RF2XX_XAH_CTRL_2__ARET_CSMA_RETRIES_OFFSET (1)
487#endif
494#define AT86RF2XX_CSMA_SEED_1__AACK_SET_PD (0x20)
495#define AT86RF2XX_CSMA_SEED_1__AACK_DIS_ACK (0x10)
496#define AT86RF2XX_CSMA_SEED_1__AACK_I_AM_COORD (0x08)
497#define AT86RF2XX_CSMA_SEED_1__CSMA_SEED_1 (0x07)
504#if defined(MODULE_AT86RFA1) || defined(MODULE_AT86RFR2)
505#define AT86RF2XX_TRXPR_ATBE (0x08)
506#define AT86RF2XX_TRXPR_TRXTST (0x04)
507#define AT86RF2XX_TRXPR_SLPTR (0x02)
508#define AT86RF2XX_TRXPR_TRXRST (0x01)
509#endif
516#ifdef MODULE_AT86RF212B
517#define AT86RF2XX_RF_CTRL_0_MASK__PA_LT (0xC0)
518#define AT86RF2XX_RF_CTRL_0_MASK__GC_TX_OFFS (0x03)
519
520#define AT86RF2XX_RF_CTRL_0_GC_TX_OFFS__0DB (0x01)
521#define AT86RF2XX_RF_CTRL_0_GC_TX_OFFS__1DB (0x02)
522#define AT86RF2XX_RF_CTRL_0_GC_TX_OFFS__2DB (0x03)
523#endif
530#define AT86RF2XX_TRX_RPC_MASK__RX_RPC_CTRL_MAXPWR (0xC0)
531#define AT86RF2XX_TRX_RPC_MASK__RX_RPC_EN (0x20)
532#define AT86RF2XX_TRX_RPC_MASK__PDT_RPC_EN (0x10)
533#define AT86RF2XX_TRX_RPC_MASK__PLL_RPC_EN (0x08)
534#define AT86RF2XX_TRX_RPC_MASK__XAH_TX_RPC_EN (0x04)
535#define AT86RF2XX_TRX_RPC_MASK__IPAN_RPC_EN (0x02)
541#define AT86RF2XX_TRX_RPC_MASK__RX_RPC__SMART_IDLE \
542 (AT86RF2XX_TRX_RPC_MASK__RX_RPC_EN \
543 | AT86RF2XX_TRX_RPC_MASK__PDT_RPC_EN \
544 | AT86RF2XX_TRX_RPC_MASK__PLL_RPC_EN \
545 | AT86RF2XX_TRX_RPC_MASK__XAH_TX_RPC_EN \
546 | AT86RF2XX_TRX_RPC_MASK__IPAN_RPC_EN)
547
548#ifdef __cplusplus
549}
550#endif
551
552#endif /* AT86RF2XX_REGISTERS_H */
Interface definition for AT86RF2xx based drivers.