at86rf2xx_registers.h
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1 /*
2  * Copyright (C) 2013 Alaeddine Weslati <alaeddine.weslati@inria.fr>
3  * Copyright (C) 2015 Freie Universit├Ąt Berlin
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
24 #ifndef AT86RF2XX_REGISTERS_H
25 #define AT86RF2XX_REGISTERS_H
26 
27 #include "at86rf2xx.h"
28 
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32 
37 #define AT86RF212B_PARTNUM (0x07)
38 #define AT86RF231_PARTNUM (0x03)
39 #define AT86RF232_PARTNUM (0x0a)
40 #define AT86RF233_PARTNUM (0x0b)
41 
47 #ifdef MODULE_AT86RF212B
48 #define AT86RF2XX_PARTNUM AT86RF212B_PARTNUM
49 #elif MODULE_AT86RF232
50 #define AT86RF2XX_PARTNUM AT86RF232_PARTNUM
51 #elif MODULE_AT86RF233
52 #define AT86RF2XX_PARTNUM AT86RF233_PARTNUM
53 #else /* MODULE_AT86RF231 as default device */
54 #define AT86RF2XX_PARTNUM AT86RF231_PARTNUM
55 #endif
56 
62 #define AT86RF2XX_ACCESS_REG (0x80)
63 #define AT86RF2XX_ACCESS_FB (0x20)
64 #define AT86RF2XX_ACCESS_SRAM (0x00)
65 #define AT86RF2XX_ACCESS_READ (0x00)
66 #define AT86RF2XX_ACCESS_WRITE (0x40)
67 
73 #define AT86RF2XX_REG__TRX_STATUS (0x01)
74 #define AT86RF2XX_REG__TRX_STATE (0x02)
75 #define AT86RF2XX_REG__TRX_CTRL_0 (0x03)
76 #define AT86RF2XX_REG__TRX_CTRL_1 (0x04)
77 #define AT86RF2XX_REG__PHY_TX_PWR (0x05)
78 #define AT86RF2XX_REG__PHY_RSSI (0x06)
79 #define AT86RF2XX_REG__PHY_ED_LEVEL (0x07)
80 #define AT86RF2XX_REG__PHY_CC_CCA (0x08)
81 #define AT86RF2XX_REG__CCA_THRES (0x09)
82 #define AT86RF2XX_REG__RX_CTRL (0x0A)
83 #define AT86RF2XX_REG__SFD_VALUE (0x0B)
84 #define AT86RF2XX_REG__TRX_CTRL_2 (0x0C)
85 #define AT86RF2XX_REG__ANT_DIV (0x0D)
86 #define AT86RF2XX_REG__IRQ_MASK (0x0E)
87 #define AT86RF2XX_REG__IRQ_STATUS (0x0F)
88 #define AT86RF2XX_REG__VREG_CTRL (0x10)
89 #define AT86RF2XX_REG__BATMON (0x11)
90 #define AT86RF2XX_REG__XOSC_CTRL (0x12)
91 #define AT86RF2XX_REG__CC_CTRL_1 (0x14)
92 #define AT86RF2XX_REG__RX_SYN (0x15)
93 #ifdef MODULE_AT86RF212B
94 #define AT86RF2XX_REG__RF_CTRL_0 (0x16)
95 #endif
96 #define AT86RF2XX_REG__XAH_CTRL_1 (0x17)
97 #define AT86RF2XX_REG__FTN_CTRL (0x18)
98 #if AT86RF2XX_HAVE_RETRIES
99 #define AT86RF2XX_REG__XAH_CTRL_2 (0x19)
100 #endif
101 #define AT86RF2XX_REG__PLL_CF (0x1A)
102 #define AT86RF2XX_REG__PLL_DCU (0x1B)
103 #define AT86RF2XX_REG__PART_NUM (0x1C)
104 #define AT86RF2XX_REG__VERSION_NUM (0x1D)
105 #define AT86RF2XX_REG__MAN_ID_0 (0x1E)
106 #define AT86RF2XX_REG__MAN_ID_1 (0x1F)
107 #define AT86RF2XX_REG__SHORT_ADDR_0 (0x20)
108 #define AT86RF2XX_REG__SHORT_ADDR_1 (0x21)
109 #define AT86RF2XX_REG__PAN_ID_0 (0x22)
110 #define AT86RF2XX_REG__PAN_ID_1 (0x23)
111 #define AT86RF2XX_REG__IEEE_ADDR_0 (0x24)
112 #define AT86RF2XX_REG__IEEE_ADDR_1 (0x25)
113 #define AT86RF2XX_REG__IEEE_ADDR_2 (0x26)
114 #define AT86RF2XX_REG__IEEE_ADDR_3 (0x27)
115 #define AT86RF2XX_REG__IEEE_ADDR_4 (0x28)
116 #define AT86RF2XX_REG__IEEE_ADDR_5 (0x29)
117 #define AT86RF2XX_REG__IEEE_ADDR_6 (0x2A)
118 #define AT86RF2XX_REG__IEEE_ADDR_7 (0x2B)
119 #define AT86RF2XX_REG__XAH_CTRL_0 (0x2C)
120 #define AT86RF2XX_REG__CSMA_SEED_0 (0x2D)
121 #define AT86RF2XX_REG__CSMA_SEED_1 (0x2E)
122 #define AT86RF2XX_REG__CSMA_BE (0x2F)
123 #define AT86RF2XX_REG__TST_CTRL_DIGI (0x36)
124 
130 #define AT86RF2XX_TRX_CTRL_0_MASK__PAD_IO (0xC0)
131 #define AT86RF2XX_TRX_CTRL_0_MASK__PAD_IO_CLKM (0x30)
132 #define AT86RF2XX_TRX_CTRL_0_MASK__CLKM_SHA_SEL (0x08)
133 #define AT86RF2XX_TRX_CTRL_0_MASK__CLKM_CTRL (0x07)
134 
135 #define AT86RF2XX_TRX_CTRL_0_DEFAULT__PAD_IO (0x00)
136 #define AT86RF2XX_TRX_CTRL_0_DEFAULT__PAD_IO_CLKM (0x10)
137 #define AT86RF2XX_TRX_CTRL_0_DEFAULT__CLKM_SHA_SEL (0x08)
138 #define AT86RF2XX_TRX_CTRL_0_DEFAULT__CLKM_CTRL (0x01)
139 
140 #define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__OFF (0x00)
141 #define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__1MHz (0x01)
142 #define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__2MHz (0x02)
143 #define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__4MHz (0x03)
144 #define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__8MHz (0x04)
145 #define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__16MHz (0x05)
146 #define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__250kHz (0x06)
147 #define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__62_5kHz (0x07)
148 
154 #define AT86RF2XX_TRX_CTRL_1_MASK__PA_EXT_EN (0x80)
155 #define AT86RF2XX_TRX_CTRL_1_MASK__IRQ_2_EXT_EN (0x40)
156 #define AT86RF2XX_TRX_CTRL_1_MASK__TX_AUTO_CRC_ON (0x20)
157 #define AT86RF2XX_TRX_CTRL_1_MASK__RX_BL_CTRL (0x10)
158 #define AT86RF2XX_TRX_CTRL_1_MASK__SPI_CMD_MODE (0x0C)
159 #define AT86RF2XX_TRX_CTRL_1_MASK__IRQ_MASK_MODE (0x02)
160 #define AT86RF2XX_TRX_CTRL_1_MASK__IRQ_POLARITY (0x01)
161 
167 #define AT86RF2XX_TRX_CTRL_2_MASK__RX_SAFE_MODE (0x80)
168 #define AT86RF2XX_TRX_CTRL_2_MASK__FREQ_MODE (0x3F)
169 #define AT86RF2XX_TRX_CTRL_2_MASK__TRX_OFF_AVDD_EN (0x40)
170 #define AT86RF2XX_TRX_CTRL_2_MASK__OQPSK_SCRAM_EN (0x20)
171 #define AT86RF2XX_TRX_CTRL_2_MASK__ALT_SPECTRUM (0x10)
172 #define AT86RF2XX_TRX_CTRL_2_MASK__BPSK_OQPSK (0x08)
173 #define AT86RF2XX_TRX_CTRL_2_MASK__SUB_MODE (0x04)
174 #define AT86RF2XX_TRX_CTRL_2_MASK__OQPSK_DATA_RATE (0x03)
175 
181 #define AT86RF2XX_IRQ_STATUS_MASK__BAT_LOW (0x80)
182 #define AT86RF2XX_IRQ_STATUS_MASK__TRX_UR (0x40)
183 #define AT86RF2XX_IRQ_STATUS_MASK__AMI (0x20)
184 #define AT86RF2XX_IRQ_STATUS_MASK__CCA_ED_DONE (0x10)
185 #define AT86RF2XX_IRQ_STATUS_MASK__TRX_END (0x08)
186 #define AT86RF2XX_IRQ_STATUS_MASK__RX_START (0x04)
187 #define AT86RF2XX_IRQ_STATUS_MASK__PLL_UNLOCK (0x02)
188 #define AT86RF2XX_IRQ_STATUS_MASK__PLL_LOCK (0x01)
189 
195 #define AT86RF2XX_TRX_STATUS_MASK__CCA_DONE (0x80)
196 #define AT86RF2XX_TRX_STATUS_MASK__CCA_STATUS (0x40)
197 #define AT86RF2XX_TRX_STATUS_MASK__TRX_STATUS (0x1F)
198 
199 #define AT86RF2XX_TRX_STATUS__P_ON (0x00)
200 #define AT86RF2XX_TRX_STATUS__BUSY_RX (0x01)
201 #define AT86RF2XX_TRX_STATUS__BUSY_TX (0x02)
202 #define AT86RF2XX_TRX_STATUS__RX_ON (0x06)
203 #define AT86RF2XX_TRX_STATUS__TRX_OFF (0x08)
204 #define AT86RF2XX_TRX_STATUS__PLL_ON (0x09)
205 #define AT86RF2XX_TRX_STATUS__SLEEP (0x0F)
206 #define AT86RF2XX_TRX_STATUS__BUSY_RX_AACK (0x11)
207 #define AT86RF2XX_TRX_STATUS__BUSY_TX_ARET (0x12)
208 #define AT86RF2XX_TRX_STATUS__RX_AACK_ON (0x16)
209 #define AT86RF2XX_TRX_STATUS__TX_ARET_ON (0x19)
210 #define AT86RF2XX_TRX_STATUS__RX_ON_NOCLK (0x1C)
211 #define AT86RF2XX_TRX_STATUS__RX_AACK_ON_NOCLK (0x1D)
212 #define AT86RF2XX_TRX_STATUS__BUSY_RX_AACK_NOCLK (0x1E)
213 #define AT86RF2XX_TRX_STATUS__STATE_TRANSITION_IN_PROGRESS (0x1F)
214 
220 #define AT86RF2XX_TRX_STATE_MASK__TRAC (0xe0)
221 
222 #define AT86RF2XX_TRX_STATE__NOP (0x00)
223 #define AT86RF2XX_TRX_STATE__TX_START (0x02)
224 #define AT86RF2XX_TRX_STATE__FORCE_TRX_OFF (0x03)
225 #define AT86RF2XX_TRX_STATE__FORCE_PLL_ON (0x04)
226 #define AT86RF2XX_TRX_STATE__RX_ON (0x06)
227 #define AT86RF2XX_TRX_STATE__TRX_OFF (0x08)
228 #define AT86RF2XX_TRX_STATE__PLL_ON (0x09)
229 #define AT86RF2XX_TRX_STATE__RX_AACK_ON (0x16)
230 #define AT86RF2XX_TRX_STATE__TX_ARET_ON (0x19)
231 #define AT86RF2XX_TRX_STATE__TRAC_SUCCESS (0x00)
232 #define AT86RF2XX_TRX_STATE__TRAC_SUCCESS_DATA_PENDING (0x20)
233 #define AT86RF2XX_TRX_STATE__TRAC_SUCCESS_WAIT_FOR_ACK (0x40)
234 #define AT86RF2XX_TRX_STATE__TRAC_CHANNEL_ACCESS_FAILURE (0x60)
235 #define AT86RF2XX_TRX_STATE__TRAC_NO_ACK (0xa0)
236 #define AT86RF2XX_TRX_STATE__TRAC_INVALID (0xe0)
237 
243 #define AT86RF2XX_PHY_CC_CCA_MASK__CCA_REQUEST (0x80)
244 #define AT86RF2XX_PHY_CC_CCA_MASK__CCA_MODE (0x60)
245 #define AT86RF2XX_PHY_CC_CCA_MASK__CHANNEL (0x1F)
246 
247 #define AT86RF2XX_PHY_CC_CCA_DEFAULT__CCA_MODE (0x20)
248 
254 #define AT86RF2XX_CCA_THRES_MASK__CCA_ED_THRES (0x0F)
255 
256 #define AT86RF2XX_CCA_THRES_MASK__RSVD_HI_NIBBLE (0xC0)
257 
263 #ifdef MODULE_AT86RF212B
264 #define AT86RF2XX_PHY_TX_PWR_MASK__PA_BOOST (0x80)
265 #define AT86RF2XX_PHY_TX_PWR_MASK__GC_PA (0x60)
266 #define AT86RF2XX_PHY_TX_PWR_MASK__TX_PWR (0x1F)
267 #elif MODULE_AT86RF231
268 #define AT86RF2XX_PHY_TX_PWR_MASK__PA_BUF_LT (0xC0)
269 #define AT86RF2XX_PHY_TX_PWR_MASK__PA_LT (0x30)
270 #define AT86RF2XX_PHY_TX_PWR_MASK__TX_PWR (0x0F)
271 #else
272 #define AT86RF2XX_PHY_TX_PWR_MASK__TX_PWR (0x0F)
273 #endif
274 #define AT86RF2XX_PHY_TX_PWR_DEFAULT__PA_BUF_LT (0xC0)
275 #define AT86RF2XX_PHY_TX_PWR_DEFAULT__PA_LT (0x00)
276 #define AT86RF2XX_PHY_TX_PWR_DEFAULT__TX_PWR (0x00)
277 
283 #define AT86RF2XX_PHY_RSSI_MASK__RX_CRC_VALID (0x80)
284 #define AT86RF2XX_PHY_RSSI_MASK__RND_VALUE (0x60)
285 #define AT86RF2XX_PHY_RSSI_MASK__RSSI (0x1F)
286 
292 #define AT86RF2XX_XOSC_CTRL__XTAL_MODE_CRYSTAL (0xF0)
293 #define AT86RF2XX_XOSC_CTRL__XTAL_MODE_EXTERNAL (0xF0)
294 
300 #define AT86RF2XX_RX_SYN__RX_PDT_DIS (0x80)
301 #define AT86RF2XX_RX_SYN__RX_OVERRIDE (0x70)
302 #define AT86RF2XX_RX_SYN__RX_PDT_LEVEL (0x0F)
303 
309 #define AT86RF2XX_TIMING__VCC_TO_P_ON (330)
310 #define AT86RF2XX_TIMING__SLEEP_TO_TRX_OFF (380)
311 #define AT86RF2XX_TIMING__TRX_OFF_TO_PLL_ON (110)
312 #define AT86RF2XX_TIMING__TRX_OFF_TO_RX_ON (110)
313 #define AT86RF2XX_TIMING__PLL_ON_TO_BUSY_TX (16)
314 #define AT86RF2XX_TIMING__RESET (100)
315 #define AT86RF2XX_TIMING__RESET_TO_TRX_OFF (37)
316 
322 #define AT86RF2XX_XAH_CTRL_0__MAX_FRAME_RETRIES (0xF0)
323 #define AT86RF2XX_XAH_CTRL_0__MAX_CSMA_RETRIES (0x0E)
324 #define AT86RF2XX_XAH_CTRL_0__SLOTTED_OPERATION (0x01)
325 
331 #define AT86RF2XX_XAH_CTRL_1__AACK_FLTR_RES_FT (0x20)
332 #define AT86RF2XX_XAH_CTRL_1__AACK_UPLD_RES_FT (0x10)
333 #define AT86RF2XX_XAH_CTRL_1__AACK_ACK_TIME (0x04)
334 #define AT86RF2XX_XAH_CTRL_1__AACK_PROM_MODE (0x02)
335 
346 #if AT86RF2XX_HAVE_RETRIES
347 #define AT86RF2XX_XAH_CTRL_2__ARET_FRAME_RETRIES_MASK (0xF0)
348 #define AT86RF2XX_XAH_CTRL_2__ARET_FRAME_RETRIES_OFFSET (4)
349 #define AT86RF2XX_XAH_CTRL_2__ARET_CSMA_RETRIES_MASK (0x0E)
350 #define AT86RF2XX_XAH_CTRL_2__ARET_CSMA_RETRIES_OFFSET (1)
351 #endif
352 
358 #define AT86RF2XX_CSMA_SEED_1__AACK_SET_PD (0x20)
359 #define AT86RF2XX_CSMA_SEED_1__AACK_DIS_ACK (0x10)
360 #define AT86RF2XX_CSMA_SEED_1__AACK_I_AM_COORD (0x08)
361 #define AT86RF2XX_CSMA_SEED_1__CSMA_SEED_1 (0x07)
362 
368 #ifdef MODULE_AT86RF212B
369 #define AT86RF2XX_RF_CTRL_0_MASK__PA_LT (0xC0)
370 #define AT86RF2XX_RF_CTRL_0_MASK__GC_TX_OFFS (0x03)
371 
372 #define AT86RF2XX_RF_CTRL_0_GC_TX_OFFS__0DB (0x01)
373 #define AT86RF2XX_RF_CTRL_0_GC_TX_OFFS__1DB (0x02)
374 #define AT86RF2XX_RF_CTRL_0_GC_TX_OFFS__2DB (0x03)
375 #endif
376 
378 #ifdef __cplusplus
379 }
380 #endif
381 
382 #endif /* AT86RF2XX_REGISTERS_H */
383 
Interface definition for AT86RF2xx based drivers.