at86rf2xx_registers.h
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1 /*
2  * Copyright (C) 2013 Alaeddine Weslati <alaeddine.weslati@inria.fr>
3  * Copyright (C) 2015 Freie Universit├Ąt Berlin
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
24 #ifndef AT86RF2XX_REGISTERS_H
25 #define AT86RF2XX_REGISTERS_H
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30 
35 #define AT86RF212B_PARTNUM (0x07)
36 #define AT86RF231_PARTNUM (0x03)
37 #define AT86RF232_PARTNUM (0x0a)
38 #define AT86RF233_PARTNUM (0x0b)
39 
45 #ifdef MODULE_AT86RF212B
46 #define AT86RF2XX_PARTNUM AT86RF212B_PARTNUM
47 #elif MODULE_AT86RF232
48 #define AT86RF2XX_PARTNUM AT86RF232_PARTNUM
49 #elif MODULE_AT86RF233
50 #define AT86RF2XX_PARTNUM AT86RF233_PARTNUM
51 #else /* MODULE_AT86RF231 as default device */
52 #define AT86RF2XX_PARTNUM AT86RF231_PARTNUM
53 #endif
54 
60 #define AT86RF2XX_ACCESS_REG (0x80)
61 #define AT86RF2XX_ACCESS_FB (0x20)
62 #define AT86RF2XX_ACCESS_SRAM (0x00)
63 #define AT86RF2XX_ACCESS_READ (0x00)
64 #define AT86RF2XX_ACCESS_WRITE (0x40)
65 
71 #define AT86RF2XX_REG__TRX_STATUS (0x01)
72 #define AT86RF2XX_REG__TRX_STATE (0x02)
73 #define AT86RF2XX_REG__TRX_CTRL_0 (0x03)
74 #define AT86RF2XX_REG__TRX_CTRL_1 (0x04)
75 #define AT86RF2XX_REG__PHY_TX_PWR (0x05)
76 #define AT86RF2XX_REG__PHY_RSSI (0x06)
77 #define AT86RF2XX_REG__PHY_ED_LEVEL (0x07)
78 #define AT86RF2XX_REG__PHY_CC_CCA (0x08)
79 #define AT86RF2XX_REG__CCA_THRES (0x09)
80 #define AT86RF2XX_REG__RX_CTRL (0x0A)
81 #define AT86RF2XX_REG__SFD_VALUE (0x0B)
82 #define AT86RF2XX_REG__TRX_CTRL_2 (0x0C)
83 #define AT86RF2XX_REG__ANT_DIV (0x0D)
84 #define AT86RF2XX_REG__IRQ_MASK (0x0E)
85 #define AT86RF2XX_REG__IRQ_STATUS (0x0F)
86 #define AT86RF2XX_REG__VREG_CTRL (0x10)
87 #define AT86RF2XX_REG__BATMON (0x11)
88 #define AT86RF2XX_REG__XOSC_CTRL (0x12)
89 #define AT86RF2XX_REG__CC_CTRL_1 (0x14)
90 #define AT86RF2XX_REG__RX_SYN (0x15)
91 #ifdef MODULE_AT86RF212B
92 #define AT86RF2XX_REG__RF_CTRL_0 (0x16)
93 #endif
94 #define AT86RF2XX_REG__XAH_CTRL_1 (0x17)
95 #define AT86RF2XX_REG__FTN_CTRL (0x18)
96 #define AT86RF2XX_REG__PLL_CF (0x1A)
97 #define AT86RF2XX_REG__PLL_DCU (0x1B)
98 #define AT86RF2XX_REG__PART_NUM (0x1C)
99 #define AT86RF2XX_REG__VERSION_NUM (0x1D)
100 #define AT86RF2XX_REG__MAN_ID_0 (0x1E)
101 #define AT86RF2XX_REG__MAN_ID_1 (0x1F)
102 #define AT86RF2XX_REG__SHORT_ADDR_0 (0x20)
103 #define AT86RF2XX_REG__SHORT_ADDR_1 (0x21)
104 #define AT86RF2XX_REG__PAN_ID_0 (0x22)
105 #define AT86RF2XX_REG__PAN_ID_1 (0x23)
106 #define AT86RF2XX_REG__IEEE_ADDR_0 (0x24)
107 #define AT86RF2XX_REG__IEEE_ADDR_1 (0x25)
108 #define AT86RF2XX_REG__IEEE_ADDR_2 (0x26)
109 #define AT86RF2XX_REG__IEEE_ADDR_3 (0x27)
110 #define AT86RF2XX_REG__IEEE_ADDR_4 (0x28)
111 #define AT86RF2XX_REG__IEEE_ADDR_5 (0x29)
112 #define AT86RF2XX_REG__IEEE_ADDR_6 (0x2A)
113 #define AT86RF2XX_REG__IEEE_ADDR_7 (0x2B)
114 #define AT86RF2XX_REG__XAH_CTRL_0 (0x2C)
115 #define AT86RF2XX_REG__CSMA_SEED_0 (0x2D)
116 #define AT86RF2XX_REG__CSMA_SEED_1 (0x2E)
117 #define AT86RF2XX_REG__CSMA_BE (0x2F)
118 #define AT86RF2XX_REG__TST_CTRL_DIGI (0x36)
119 
125 #define AT86RF2XX_TRX_CTRL_0_MASK__PAD_IO (0xC0)
126 #define AT86RF2XX_TRX_CTRL_0_MASK__PAD_IO_CLKM (0x30)
127 #define AT86RF2XX_TRX_CTRL_0_MASK__CLKM_SHA_SEL (0x08)
128 #define AT86RF2XX_TRX_CTRL_0_MASK__CLKM_CTRL (0x07)
129 
130 #define AT86RF2XX_TRX_CTRL_0_DEFAULT__PAD_IO (0x00)
131 #define AT86RF2XX_TRX_CTRL_0_DEFAULT__PAD_IO_CLKM (0x10)
132 #define AT86RF2XX_TRX_CTRL_0_DEFAULT__CLKM_SHA_SEL (0x08)
133 #define AT86RF2XX_TRX_CTRL_0_DEFAULT__CLKM_CTRL (0x01)
134 
135 #define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__OFF (0x00)
136 #define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__1MHz (0x01)
137 #define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__2MHz (0x02)
138 #define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__4MHz (0x03)
139 #define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__8MHz (0x04)
140 #define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__16MHz (0x05)
141 #define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__250kHz (0x06)
142 #define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__62_5kHz (0x07)
143 
149 #define AT86RF2XX_TRX_CTRL_1_MASK__PA_EXT_EN (0x80)
150 #define AT86RF2XX_TRX_CTRL_1_MASK__IRQ_2_EXT_EN (0x40)
151 #define AT86RF2XX_TRX_CTRL_1_MASK__TX_AUTO_CRC_ON (0x20)
152 #define AT86RF2XX_TRX_CTRL_1_MASK__RX_BL_CTRL (0x10)
153 #define AT86RF2XX_TRX_CTRL_1_MASK__SPI_CMD_MODE (0x0C)
154 #define AT86RF2XX_TRX_CTRL_1_MASK__IRQ_MASK_MODE (0x02)
155 #define AT86RF2XX_TRX_CTRL_1_MASK__IRQ_POLARITY (0x01)
156 
162 #define AT86RF2XX_TRX_CTRL_2_MASK__RX_SAFE_MODE (0x80)
163 #define AT86RF2XX_TRX_CTRL_2_MASK__FREQ_MODE (0x3F)
164 #define AT86RF2XX_TRX_CTRL_2_MASK__TRX_OFF_AVDD_EN (0x40)
165 #define AT86RF2XX_TRX_CTRL_2_MASK__OQPSK_SCRAM_EN (0x20)
166 #define AT86RF2XX_TRX_CTRL_2_MASK__ALT_SPECTRUM (0x10)
167 #define AT86RF2XX_TRX_CTRL_2_MASK__BPSK_OQPSK (0x08)
168 #define AT86RF2XX_TRX_CTRL_2_MASK__SUB_MODE (0x04)
169 #define AT86RF2XX_TRX_CTRL_2_MASK__OQPSK_DATA_RATE (0x03)
170 
176 #define AT86RF2XX_IRQ_STATUS_MASK__BAT_LOW (0x80)
177 #define AT86RF2XX_IRQ_STATUS_MASK__TRX_UR (0x40)
178 #define AT86RF2XX_IRQ_STATUS_MASK__AMI (0x20)
179 #define AT86RF2XX_IRQ_STATUS_MASK__CCA_ED_DONE (0x10)
180 #define AT86RF2XX_IRQ_STATUS_MASK__TRX_END (0x08)
181 #define AT86RF2XX_IRQ_STATUS_MASK__RX_START (0x04)
182 #define AT86RF2XX_IRQ_STATUS_MASK__PLL_UNLOCK (0x02)
183 #define AT86RF2XX_IRQ_STATUS_MASK__PLL_LOCK (0x01)
184 
190 #define AT86RF2XX_TRX_STATUS_MASK__CCA_DONE (0x80)
191 #define AT86RF2XX_TRX_STATUS_MASK__CCA_STATUS (0x40)
192 #define AT86RF2XX_TRX_STATUS_MASK__TRX_STATUS (0x1F)
193 
194 #define AT86RF2XX_TRX_STATUS__P_ON (0x00)
195 #define AT86RF2XX_TRX_STATUS__BUSY_RX (0x01)
196 #define AT86RF2XX_TRX_STATUS__BUSY_TX (0x02)
197 #define AT86RF2XX_TRX_STATUS__RX_ON (0x06)
198 #define AT86RF2XX_TRX_STATUS__TRX_OFF (0x08)
199 #define AT86RF2XX_TRX_STATUS__PLL_ON (0x09)
200 #define AT86RF2XX_TRX_STATUS__SLEEP (0x0F)
201 #define AT86RF2XX_TRX_STATUS__BUSY_RX_AACK (0x11)
202 #define AT86RF2XX_TRX_STATUS__BUSY_TX_ARET (0x12)
203 #define AT86RF2XX_TRX_STATUS__RX_AACK_ON (0x16)
204 #define AT86RF2XX_TRX_STATUS__TX_ARET_ON (0x19)
205 #define AT86RF2XX_TRX_STATUS__RX_ON_NOCLK (0x1C)
206 #define AT86RF2XX_TRX_STATUS__RX_AACK_ON_NOCLK (0x1D)
207 #define AT86RF2XX_TRX_STATUS__BUSY_RX_AACK_NOCLK (0x1E)
208 #define AT86RF2XX_TRX_STATUS__STATE_TRANSITION_IN_PROGRESS (0x1F)
209 
215 #define AT86RF2XX_TRX_STATE_MASK__TRAC (0xe0)
216 
217 #define AT86RF2XX_TRX_STATE__NOP (0x00)
218 #define AT86RF2XX_TRX_STATE__TX_START (0x02)
219 #define AT86RF2XX_TRX_STATE__FORCE_TRX_OFF (0x03)
220 #define AT86RF2XX_TRX_STATE__FORCE_PLL_ON (0x04)
221 #define AT86RF2XX_TRX_STATE__RX_ON (0x06)
222 #define AT86RF2XX_TRX_STATE__TRX_OFF (0x08)
223 #define AT86RF2XX_TRX_STATE__PLL_ON (0x09)
224 #define AT86RF2XX_TRX_STATE__RX_AACK_ON (0x16)
225 #define AT86RF2XX_TRX_STATE__TX_ARET_ON (0x19)
226 #define AT86RF2XX_TRX_STATE__TRAC_SUCCESS (0x00)
227 #define AT86RF2XX_TRX_STATE__TRAC_SUCCESS_DATA_PENDING (0x20)
228 #define AT86RF2XX_TRX_STATE__TRAC_SUCCESS_WAIT_FOR_ACK (0x40)
229 #define AT86RF2XX_TRX_STATE__TRAC_CHANNEL_ACCESS_FAILURE (0x60)
230 #define AT86RF2XX_TRX_STATE__TRAC_NO_ACK (0xa0)
231 #define AT86RF2XX_TRX_STATE__TRAC_INVALID (0xe0)
232 
238 #define AT86RF2XX_PHY_CC_CCA_MASK__CCA_REQUEST (0x80)
239 #define AT86RF2XX_PHY_CC_CCA_MASK__CCA_MODE (0x60)
240 #define AT86RF2XX_PHY_CC_CCA_MASK__CHANNEL (0x1F)
241 
242 #define AT86RF2XX_PHY_CC_CCA_DEFAULT__CCA_MODE (0x20)
243 
249 #define AT86RF2XX_CCA_THRES_MASK__CCA_ED_THRES (0x0F)
250 
251 #define AT86RF2XX_CCA_THRES_MASK__RSVD_HI_NIBBLE (0xC0)
252 
258 #ifdef MODULE_AT86RF212B
259 #define AT86RF2XX_PHY_TX_PWR_MASK__PA_BOOST (0x80)
260 #define AT86RF2XX_PHY_TX_PWR_MASK__GC_PA (0x60)
261 #define AT86RF2XX_PHY_TX_PWR_MASK__TX_PWR (0x1F)
262 #elif MODULE_AT86RF231
263 #define AT86RF2XX_PHY_TX_PWR_MASK__PA_BUF_LT (0xC0)
264 #define AT86RF2XX_PHY_TX_PWR_MASK__PA_LT (0x30)
265 #define AT86RF2XX_PHY_TX_PWR_MASK__TX_PWR (0x0F)
266 #else
267 #define AT86RF2XX_PHY_TX_PWR_MASK__TX_PWR (0x0F)
268 #endif
269 #define AT86RF2XX_PHY_TX_PWR_DEFAULT__PA_BUF_LT (0xC0)
270 #define AT86RF2XX_PHY_TX_PWR_DEFAULT__PA_LT (0x00)
271 #define AT86RF2XX_PHY_TX_PWR_DEFAULT__TX_PWR (0x00)
272 
278 #define AT86RF2XX_PHY_RSSI_MASK__RX_CRC_VALID (0x80)
279 #define AT86RF2XX_PHY_RSSI_MASK__RND_VALUE (0x60)
280 #define AT86RF2XX_PHY_RSSI_MASK__RSSI (0x1F)
281 
287 #define AT86RF2XX_XOSC_CTRL__XTAL_MODE_CRYSTAL (0xF0)
288 #define AT86RF2XX_XOSC_CTRL__XTAL_MODE_EXTERNAL (0xF0)
289 
295 #define AT86RF2XX_TIMING__VCC_TO_P_ON (330)
296 #define AT86RF2XX_TIMING__SLEEP_TO_TRX_OFF (380)
297 #define AT86RF2XX_TIMING__TRX_OFF_TO_PLL_ON (110)
298 #define AT86RF2XX_TIMING__TRX_OFF_TO_RX_ON (110)
299 #define AT86RF2XX_TIMING__PLL_ON_TO_BUSY_TX (16)
300 #define AT86RF2XX_TIMING__RESET (100)
301 #define AT86RF2XX_TIMING__RESET_TO_TRX_OFF (37)
302 
308 #define AT86RF2XX_XAH_CTRL_0__MAX_FRAME_RETRIES (0xF0)
309 #define AT86RF2XX_XAH_CTRL_0__MAX_CSMA_RETRIES (0x0E)
310 #define AT86RF2XX_XAH_CTRL_0__SLOTTED_OPERATION (0x01)
311 
317 #define AT86RF2XX_XAH_CTRL_1__AACK_FLTR_RES_FT (0x20)
318 #define AT86RF2XX_XAH_CTRL_1__AACK_UPLD_RES_FT (0x10)
319 #define AT86RF2XX_XAH_CTRL_1__AACK_ACK_TIME (0x04)
320 #define AT86RF2XX_XAH_CTRL_1__AACK_PROM_MODE (0x02)
321 
327 #define AT86RF2XX_CSMA_SEED_1__AACK_SET_PD (0x20)
328 #define AT86RF2XX_CSMA_SEED_1__AACK_DIS_ACK (0x10)
329 #define AT86RF2XX_CSMA_SEED_1__AACK_I_AM_COORD (0x08)
330 #define AT86RF2XX_CSMA_SEED_1__CSMA_SEED_1 (0x07)
331 
337 #ifdef MODULE_AT86RF212B
338 #define AT86RF2XX_RF_CTRL_0_MASK__PA_LT (0xC0)
339 #define AT86RF2XX_RF_CTRL_0_MASK__GC_TX_OFFS (0x03)
340 
341 #define AT86RF2XX_RF_CTRL_0_GC_TX_OFFS__0DB (0x01)
342 #define AT86RF2XX_RF_CTRL_0_GC_TX_OFFS__1DB (0x02)
343 #define AT86RF2XX_RF_CTRL_0_GC_TX_OFFS__2DB (0x03)
344 #endif
345 
347 #ifdef __cplusplus
348 }
349 #endif
350 
351 #endif /* AT86RF2XX_REGISTERS_H */
352