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MK60-comp.h
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1 /*
2  * Copyright (C) 2015 Eistec AB
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
19 #ifndef MK60_COMP_H
20 #define MK60_COMP_H
21 
22 #ifdef __cplusplus
23 extern "C"
24 {
25 #endif
26 
27 #if K60_CPU_REV == 1
28 
29 /* Some compatibility defines to minimize the ifdefs needed for the register
30  * name changes */
31 
32 #define SIM_SCGC6_SPI0_MASK SIM_SCGC6_DSPI0_MASK
33 #define SIM_SCGC6_SPI0_SHIFT SIM_SCGC6_DSPI0_SHIFT
34 
35 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
36 #define MCG_C5_PRDIV0_MASK MCG_C5_PRDIV_MASK
37 #define MCG_C6_VDIV0_MASK MCG_C6_VDIV_MASK
38 
39 #define UART_BASES { UART0, UART1, UART2, UART3, UART4, UART5 }
40 
41 #define LPTMR0_IRQn LPTimer_IRQn
42 
43 /* Rev 2.x made the OSC32KSEL field into a bitfield (is a single bit in 1.x) */
44 #define SIM_SOPT1_OSC32KSEL(a) (SIM_SOPT1_OSC32KSEL_MASK)
45 
46 #endif /* K60_CPU_REV == 1 */
47 
48 
49 /* Compatibility defines for compatibility with differing module names between
50  * MK60 and MKW22 headers */
51 #define SIM_SCGC5_LPTMR_MASK SIM_SCGC5_LPTIMER_MASK
52 #define SIM_SCGC5_LPTMR_SHIFT SIM_SCGC5_LPTIMER_SHIFT
53 
54 #ifndef OSC0
55 /* Compatibility definition */
56 #define OSC0 OSC
57 #endif
58 #ifndef MCG_C2_RANGE0
59 /* Rev 2 parts renamed the parameter RANGE -> RANGE0 */
60 #define MCG_C2_RANGE0 MCG_C2_RANGE
61 #endif
62 
63 #ifdef __cplusplus
64 }
65 #endif
66 
67 
68 #endif /* MK60_COMP_H */
69